XC95288 FAMILY Search Results

XC95288-15HQ208I

Abstract: XC95288
Contextual Info: Product Obsolete/Under Obsolescence XC95288 In-System Programmable CPLD R DS069 v5.0 May 17, 2013 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates

10HQ

Abstract: XC95288 471 E25 HQ208 XC9500
Contextual Info: XC95288 In-System Programmable CPLD  September 15, 1999 Version 4.0 5* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

A23 780-4

Abstract: 471 E25 BG352 HQ208 XC9500 XC95288
Contextual Info: XC95288 In-System Programmable CPLD  November 12, 1997 Version 2.0 3* Preliminary Product Specification Features MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f • • • • • Where: • • • • • • • • • • • MCHP = Macrocells in high-performance mode

XC95288

Abstract: BG352 HQ208 XC9500
Contextual Info:  XC95288 In-System Programmable CPLD January, 1997 Version 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 288 macrocells with 6,400 usable gates • Up to 192 user I/O pins

AC1284

Contextual Info: KXILINX XC95288 In-System Programmable CPLD April, 1997 Version 1.0 Preliminary Product Specification Features Description • 15 ns pin-to-pin logic delays on all pins • • • • fcNT t ° MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

XC95288

Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Contextual Info: 1 XC95288 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

xc95288

Abstract: BG352 XC95288-20HQ208C XC95288-20HQ208
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.0 June 18, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC95288

Contextual Info: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

XC95288

Abstract: BG352 HQ208 XC9500 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

471 E25

Abstract: xc95288 XC95288-15HQ208I AD9318 A23 780-4 BG352 HQ208 XC9500 h3144 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.3 April 3, 2006 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

F25-F26

Contextual Info: flXILINX XC95288 In-System Programmable CPLD N o vem b er 12, 1997 V ersion 2.0 Preliminary Product Specification Features MCHp (1.7) + MC lp (0.9) + MC (0.006 mA/MHz) f • 15 ns pin-to-pin logic delays on all pins • fcNT 95 MHz • 288 macrocells with 6,400 usable gates

XC95288

Abstract: Marking af1 AF24 marking
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.2 April 15, 2005 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC95216-20PQG160I

Abstract: XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500
Contextual Info: XC95216 In-System Programmable CPLD R 5 Note: The 352-pin BGA packages are being discontinued for XC95216 devices. You cannot order these packages after May 14, 2008. Xilinx recommends replacing XC95216 in 352-pin BGA packages with XC95288 devices in 352-pin BGA packages in all designs as soon as possible. Recommended replacements are pin compatible, but

RES 364

Abstract: XC95288
Contextual Info: HXILINX XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family F eatu res. Family O verview .

XC9500XL

Abstract: XC95144 XC95288 XC9500 XC95288 Family
Contextual Info: The FastFLASH XC9500XL Advantage “.you can rest The XC9500XL 3.3V CPLD family uniquely excels in all three “ARM” criteria, and offers the highest level of programming reliability in a JTAGcompatible, in-system programmable family. The XC9500XL family features:

XC9536-PC44

Abstract: xc9572 data sheet XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 HQ208 PC44
Contextual Info: Ann Duft Xilinx, Inc. 408 879-4726 ann.duft@xilinx.com Frankie Borison Oak Ridge Public Relations (408) 253-5042 frankie@oakridge.com FOR IMMEDIATE RELEASE XILINX SHIPPING LARGEST MEMBER OF ISP CPLD FAMILY SAN JOSE, Calif., August 6, 1997—Xilinx, Inc., (NASDAQ:XLNX), today announced it has begun

XC95288

Contextual Info: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates

Contextual Info: flX IU N X XC95286 In-System Programmable CPLD November 12, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates

PQFP160 XILINX

Abstract: XC9536-44 plcc44 pinout numbers XC9500 pinout tas t23 Fuse n25 PLCC44 pinout PLCC84 package VQFP44 package XC9500 Family
Contextual Info: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction This document pertains to the following devices and packages: device addresses are contained on the included Add.dat floppy disk. Signature String 9536 - PLCC44, CSP48, and VQFP44 9572 - PLCC44, PLCC84, PQFP100,

jtag 14

Abstract: XC9500XL
Contextual Info: by Dave Chiang, Manager, CPLD Technical Marketing, david.chiang@ xilinx.com Choosing A 3.3V CPLD? “ARM” Yourself… Leading digital system manufacturers are rapidly adopting 3.3V components for higher performance, lower costs, lower power, and higher system reliability. With many new 3.3V

cpld FOOTPRINT

Abstract: XC95216 Family DS06 IN SYSTEM PROGRAMMING DATASHEET XC9500 pinout HW130 XC9500 XC95108 XC95144 XC95216
Contextual Info: k XC9500 In-System Programmable CPLD Family R DS063 v5.2 February 16, 2004 Product Specification Features - Advanced CMOS 5V Fast FLASH technology • - Supports parallel programming of multiple XC9500 devices • High-performance - 5 ns pin-to-pin logic delays on all pins

100-PIN TQFP XILINX DIMENSION

Abstract: xilinx xc9536 digital clock xc9536-pc44 XC95216XL xc95144 pin diagram XC95108XL XC9536 XC95144 XC9500 pinout XC9536XL Series
Contextual Info: Ann Duft Xilinx, Inc. 408 879-4726 publicrelations@xilinx.com Kathy Keller Oak Ridge Public Relations (408) 253-5042 kathy.keller@oakridge.com FOR IMMEDIATE RELEASE XILINX ANNOUNCES NEWEST MEMBER OF INDUSTRY’S FASTEST GROWING CPLD FAMILY New XC95144 device targets sweet spot of ISP CPLD market with lowest price per macrocell

XC9500 pinout

Abstract: AC24-AC25 Fuse n25 xilinx xc9536 XC9500 XC95108 XC95144 XC95216 XC95288 XC9536
Contextual Info: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction Signature String The device programming and verification procedures are similar to those used with standard FLASH EPROM memories. Initially, and after each erasure, all cells in the device

XC95144

Abstract: DS06 HW130 XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 xc95144 pinout
Contextual Info: k XC9500 In-System Programmable CPLD Family R DS063 v5.1 September 22, 2003 Product Specification Features - Advanced CMOS 5V Fast FLASH technology • - Supports parallel programming of multiple XC9500 devices • High-performance - 5 ns pin-to-pin logic delays on all pins