X8 ENCODER Search Results

Contextual Info: □ MN102L2403 MN102L2403 [ES Engineering Sample available] |Type 1 1 1 ROM (x8-bit/x16-bit) RAM (x8-bit/x16-bit) Maximum 16M in total (Special Register 1K included) External ROM, RAM 3K Minimum Instruction Execution Time Interrupts 100ns (at 4.5 to 5.5V, 20MHz)

LGFP128-P-1818B

Abstract: MN102L2403 SB01
Contextual Info: □ MN102L2403 MN102L24Q3 [ES Engineering Sam ple availab le] • Type ■ ROM <x8-bit / x l 6-b it) RAM (x8-bit / x16-b it) ■ Minimum Instruction Execution Time 1 Interrupts M a xim u m 16M in total (Special Register 1K included) External ROM, RAM 3K

MN102L2403

Contextual Info: □ MN102L2403 • Type 1 ROM x8-Bit/x16-Bit RAM (x8-Bit/x16-Bit) 1 Minimum Instruction Execution Time 1 Interrupts MN102L2403 [ES (Engineering Sample) available] Maximum 16 M in total (Special Register 1 K included) External ROM, RAM 3 K 100 ns (at 4.5 V to 5.5 V, 20 MHz)

qfp128p

Contextual Info: □ IVI N 1 020012A / 0012AFA / 0012-3V 1 Type M N 1 020012A | R O M x8-bit/x16-bit R A M (x8-bit/x16-bit) / 0 0 1 2 A F A / 0012-3V Maximum 16M In total (Special Register 1K, Reserve Space 3K included) External ROM, RAM | Minimum Instruction Execution Time

ados

Abstract: A008 AD03 AD04 MN102L490A
Contextual Info: □ MN102L490A MN102L490A • Type 1 ROM x8-Bit/x16-Bit External 1 RAM (x8-Bit/x16-Bit) 3K 1 Minimum Instruction Execution Time M Interrupts With Main Clock operated: 100 ns (at 4.5 V to 5.5 V, 20 MHz) •RESET «Watchdog «Tim er Counter 0 to 5 • Timer Counter 6 to 7

MN1020012

Abstract: 0 - 9 counter MN1020012A MN1020012AFA QFP128-P-1818 0012AF voltage mode pwm controler
Contextual Info: □ MN1020012A / 0012AFA / 0012-3V I Type I IVIM10 2 0 0 1 2 A / 00 1 2 AFA / 0012-3V ROM x8-bit RAM (x8-bit / X16-bit M a xim u m 16M in to ta l (Special R egister 1 K, Reserve / x16-b it) External ROM, RAM I Minimum Instruction Execution Time I Interrupts

LQFP128-P-1818B

Abstract: LQFP128 P571 MN1021213
Contextual Info: □ M N 1 0 2 1 2 1 3 1 Type • ROM x8-bit 90K 1 RAM (x8-bit) 3K 1 Minimum Instruction Execution Time M N 1Q 21213 Processor Mode 200ns (at 2 .7 to 3 .6 V , 10M H z) (H ow ever, a w a it setting of 1 w ait o r m ore is required fo r p erip h era i-fu nctio n

Contextual Info: □ MN102L2403 M N 1 0 2 L 2 4 0 3 [ E S En g ine erin g S a m p le available] • Type Maximum 16M in total (Special Register 1K included) External ROM, RAM 3K 1 R O M (x8 -b it/x16 -b it) R A M (x8 -b it/x 16 -b it) 100ns (at 4.5 to 5.5V, 20MHz) 1 M in im um Instruction Execution Tim e

PES24NT3

Abstract: 89HPES24NT3
Contextual Info: 89HPES24NT3 Product Brief 24-Lane 3-Port Non-Transparent PCI Express Switch Device Overview Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation x8, x4, x2,

MN102LP36K

Abstract: l36Z
Contextual Info: □ MN102LP36K / L36K / LP36Z / L36Z / LP36G / L36G / LP36D / L36D / L360C MN102LP36K / L36K / LP36Z / L36Z / LP36G / L36G / LP36D / L36D / L360C ES samples are available for the LP36Z and L36Z. The others are under development. I Type 1 ROM (x8-bit •

PES24NT3

Abstract: 89HPES24NT3 JESD-51
Contextual Info: 89HPES24NT3 Data Sheet 24-Lane 3-Port Non-Transparent PCI Express Switch ® Device Overview Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation x8, x4, x2,

ejtag 2.0

Contextual Info: 89HPES16T4 Data Sheet 16-Lane 4-Port PCI Express Switch Preliminary Information* Device Overview Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports

Contextual Info: □ MN102LP36K / L36K / LP36Z / L36Z / LP36G / L36G / LP36D / L36D / L360C 1 Type • ROM x8-bit/x16-bit MN102LP36K / L36K / LP36Z / L36Z / LP36G / L36G / LP36D / L36D / L36QC (ES samples are available for the LP36Z and L36Z. The others are under development.)

Lanes

Contextual Info: 89HPES24N3A Data Sheet 24-Lane 3-Port PCI Express Switch Preliminary Information* Device Overview Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports

16B 1 EEPROM

Contextual Info: 89HPES16T4 Data Sheet 16-Lane 4-Port PCI Express Switch Preliminary Information* Device Overview Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports

PES16T4

Abstract: 89PES16T4 BC484
Contextual Info: 89HPES16T4 Data Sheet 16-Lane 4-Port PCI Express Switch Preliminary Information* Device Overview Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports

Contextual Info: iC-TW4 PROGRAMMABLE INTERPOLATOR WITH AUTOMATIC OFFSET CORRECTION Rev C1, Page 1/15 FEATURES APPLICATIONS ♦ Realtime interpolation with selectable factors of x2, x4, x5, x8, x10, x16, x20, x25, x32, x50, x64 ♦ Differential signal and index gating inputs

ic-TW4

Abstract: 3 terminal hall effect rotary sensor c02 sensor G003 MV3100 MARK X32
Contextual Info: iC-TW4 PROGRAMMABLE INTERPOLATOR WITH AUTOMATIC OFFSET CORRECTION Rev D1, Page 1/14 FEATURES APPLICATIONS ♦ Realtime interpolation with selectable factors of x2, x4, x5, x8, x10, x16, x20, x25, x32, x50, x64 ♦ Differential signal and index gating inputs

u25 0501

Contextual Info: 89HPES24N3A Data Sheet 24-Lane 3-Port PCI Express Switch Preliminary Information* Device Overview Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports

OK-32K

Abstract: 28K1 D09AD
Contextual Info: □ MN102LP36K /L36K /LP36Z /L36Z /LP36G /L36G /LP36D /L36D /L360C |Type MN102LP36K / L36K / LP36Z / L36Z / LP36G / L36G / LP36D / L36D / L360C For MN102L360C are in production. LP36Z and L36Z, ES are available. The others are under development. | ROM (x8-bit/x16-bit)

Contextual Info: 89HPES24NT3 Data Sheet 24-Lane 3-Port Non-Transparent PCI Express Switch Preliminary Information* Device Overview Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation x8, x4, x2,

Contextual Info: iC-TW4 PROGRAMMABLE INTERPOLATOR WITH AUTOMATIC OFFSET CORRECTION Rev D4, Page 1/14 FEATURES APPLICATIONS ♦ Realtime interpolation with selectable factors of x2, x4, x5, x8, x10, x16, x20, x25, x32, x50, x64 ♦ Differential signal and index gating inputs

ztx a11

Abstract: PES24NT3 PCIE SWITCH IDT 89HPES24NT3 IDT M22
Contextual Info: 89HPES24NT3 Data Sheet 24-Lane 3-Port Non-Transparent PCI Express Switch Preliminary Information* ® Device Overview Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation x8, x4, x2,

Contextual Info: iC-TW4 PROGRAMMABLE INTERPOLATORliminar y WITH AUTOMATIC OFFSET CORRECTION pre Rev A2, Page 1/15 FEATURES APPLICATIONS ♦ Realtime interpolation with selectable factors of x2, x4, x5, x8, x10, x16, x20, x25, x32, x50, x64 ♦ Differential signal and index gating inputs