X36X2 Search Results

BO-35

Abstract: CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 BO35 AQ35 bq35
Contextual Info: • CY7C 43622 C Y 7C 43632/C Y 7C 43642 C Y 7C 43662/C Y 7C 43682 ¡o x o w m . m p' rVv^ ' YX xP XR F ^ P R E L IM IN A R Y 256/512/1 K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features F ully as yn ch ro n o u s and sim u ltan eo u s read an d w rite

JDS SB switch

Abstract: CY7C43644V CY7C43664V CY7C43684V CY7C43664V/CY7C43684V
Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY CYPRESS 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features — Ic c = 60 m A , lSB= 12 m A F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted FWFT Mode, Ptease See Errata Attached

Contextual Info: - ^ n n n > CYPHhbo CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY = 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted Features • H ig h -s p e ed , low -pow er, b id irec tio n al, First-In First-O ut

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

ry 8412

Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 PRELIMINARY 256/512/1 K/4K/16K x36 x2 Bidirectional Synch ronous FIFO w/ Bus Matching Features F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted H ig h -s p e ed , low -pow er, b id ire c tio n a l, first-in first-o u t

C4368

Contextual Info: CY7C43622 C Y7 C43632/C Y7 C43642 C Y7 C43662/C Y7 C43682 PRELIMINARY 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted H ig h -s p e ed , low -pow er, b id ire c tio n a l, first-in first-o u t

FullFlex36

Abstract: 2BE6
Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Abstract: TMS 1070 NL
Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

BE5L

Abstract: FullFlex36 680nA TMS 1070 NL M/CYDD09S72V18
Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

JN U10

Abstract: CY7C43624 CY7C43634 CY7C43644 CY7C43664 CY7C43684 bq35
Contextual Info: C Y 7C 43624 C Y 7C 43634/C Y 7C 43644 C Y 7C 43664/C Y 7C 43684 P R E L IM IN A R Y w •tiimttrnjÉÉÉÉÉÉÉt m s¿ *c Y éé P.1 . Xn. * . FI . Ì . . S' ï 256/512/1 K/4K/16K x36 x2 Bidirectional Synchronous FIFO w / Bus M atching Features F ully as yn ch ro n o u s and sim u ltan eo u s read an d w rite

BQ JN

Abstract: AI835 CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 TSX CSA
Contextual Info: V H M IM M K 5 S Æ ÊÊÊt ' g J rto ji? » ' P Y PRELIMINARY > » w i' jf * w p p p Q CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 fl 4 « Sw v $ w » J fifi x S 5? <? S i ^ ~ = ^ 2 5 6 / 5 1 2 / 1 K / 4 K / 1 6 K x 3 6 x 2 B id ire c tio n a l S y n c h ro n o u s FIFO

Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 y«^5558S8S88&ik, PRELIMINARY 256/512/1 K/4K/16K x36 x2 Bidirectional Synch ronous FIFO w/ Bus Matching Fully as y n c h ro n o u s and sim u ltan eo u s read and w rite o p eratio n perm itted Features • H ig h -sp eed , low -pow er, B id irectio n al, First-In F irst-O u t

bb 3527

Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching • Fully as yn ch ro n o u s and sim u ltan eo u s read and w rite o p eratio n p erm itted Features • 3.3 V h ig h -sp eed , low -pow er, b id irec tio n al, first-in

FullFlex36

Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port