VIRTUAL MEMORY PROCESSING UNIT Search Results

ic 40 pin

Abstract: Z8000 Z8003 Z8004 LDB 107
Contextual Info: Virtual Memory Processing Unit Features • Regular, easy-to-use architecture. ■ Instruction set more powerful than many minicomputers. ■ Direct addressing capability of up to 8M bytes in each address space. ■ Supports implementation of virtual memory systems.

MC68376

Contextual Info: MOTOROLA Order this document by MC68336/376PP/D SEMICONDUCTOR TECHNICAL DATA MC68336/376 Product Preview 32-Bit Modular Microcontroller Features • Central Processing Unit CPU32 — 32-bit architecture — Virtual memory implementation — Table look-up and interpolate instruction

ZE003

Abstract: ZE004 Z8003 Z8000 Virtual Memory Processing Unit sda 2084 z8001 Z8004 z8010 AD0-AD15
Contextual Info: Z 8003/4 Z8000 VMPU Virtual Memory Processing Unit 17: « Product Specification A pril 1985 • Regular, easy-to-use architecture. ■ Separate System and Normal operating modes. ■ Instruction set more powerful than many minicomputers. ■ Sophisticated interrupt structure.

TDA 1111 sp

Contextual Info: Z8003/4 Z8000 VMPU Virtual Memory Processing Unit ;« ¿• llO CJ Product Specification 17 April 1985 ■ Regular, easy-to-use architecture. ■ Separate System and Normal operating modes. ■ Instruction set more powerful than many minicomputers. ■ Sophisticated interrupt structure.

CL1226

Abstract: Fujitsu SPARC
Contextual Info: F U JIT SU SPARC Memory Management Unit MB86920 FEATURES: • Compatible with the SPARC Reference MMU • Page level protections • 32-bit virtual address, 36-bit physical address • Selective flu shing and probing • Fixed 4K-byte page size • Hardware miss-processing

Z8003ACE

Abstract: Z8003 tda 2084
Contextual Info: ZILOG INC 75 DEB T O M D 4 3 DDOSSSt. 2 I T ~ W 7 W k Z 8003/4 Z8000 VMPU Virtual Memory Processing Unit Zilog Product Specification A p r il 1985 • Regular, easy-to-use architecture. Separate System and Normal operating modes. ■ Instruction set more powerful than many minicomputers.

R2000

Abstract: R3000 R3000A TX39 0000-0x7EFF dalc mark
Contextual Info: Architecture Î^ B /lc m T O S H IB A Chapter 5 Memory Management Unit TX39/H2 Processor Core has two virtual address mapping mode, direct segment mapping and TLB address mapping See product manual for setting . 5.1 TX39 P rocessor Core O perating Modes The TX39/H2 Processor Core has two operating modes, user mode and kernel mode.

Contextual Info: C h a p te r 6 CPU Exception Processing Notes Introduction This chapter describes the CPU exception processing, discusses the format and use of each CPU exception register and concludes with a description of each exception's cause as well as CPU service procedures. For information about Floating-Point Unit exceptions, refer to Chapter 7.

M68000

Abstract: MC68020 MC68030 MC68881 MC68882 MC68020 programming
Contextual Info: SECTION 1 INTRODUCTION The MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola. The MC68030 is a member of the M68000 Family of devices that combines a central processing unit CPU core, a data cache, an instruction cache, an enhanced bus controller,

IBM processor

Abstract: 65Z5 IBM2520L8767 93-620R2 CRM 1191A 93-727 BC 247 RISCwatch BIOS chip 0d19
Contextual Info: â IBM Processor for ATM Resources Revision 2.1 Databook â Copyright and Disclaimer  Copyright International Business Machines Corporation 1999 All Rights Reserved Printed in the United States of America August 1999 The following are trademarks of International Business Machines Corporation in the United States, or other countries,

CRM 1191A

Abstract: of RAS 0510 relay ras 0610 relay PIN CONFIGURATION relay RAS 0510 RISCwatch
Contextual Info:  ATM Resource Manager Revision 2.1 Databook   International Business Machines Corp.1992-1998 Copyright and Disclaimer Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation.

MC88110

Abstract: motorola 88000 MC88100 MC88410 MC88110RC MC88200 M88000 mc88204rc 88000 stream register cache coherency
Contextual Info: The M88000 RISC Family In Brief . . . Page Architecture, Performance, and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . 2.3–2 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3–2 Cache/Memory Management Units . . . . . . . . . . . . . . . 2.3–3

digital cross connect

Abstract: 7486 motorola single stage grooming pll 4046
Contextual Info: Viti-48 SONET/SDH Tributary Digital Cross Connect Features • A single stage, non-blocking time switch for cross-connecting virtual tributaries VTs or tributary units (TUs) with an aggregate bandwidth of 2488 Mbps • Provides for cross-connection across sixteen

date code marking intel strataflash 128

Abstract: IXDP425 CP15 IXC1100 IXP425 IXP42X traffic light controller microprocessor 0xC4000000
Contextual Info: Intel IXP42X Product Line and IXC1100 Control Plane Processor: Memory Management Unit and Cache Operation Application Note July 2004 Order Number: 252676-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS

x0606

Abstract: IBM processor X219 MCI 7801 162024 10E431 SOH-A2 312402
Contextual Info:  IBM Processor for Network Resources Version 2.6 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America March 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries,

Cy7C601

Abstract: CY7C605 c5wg
Contextual Info: 4t.E D CYPRESS SEMICONDUCTOR El H S Ö i L b a 0 0 0 7 4 0 4 S S3 CYP CY7C605A -_-ra ¿rar y — zr^r CYPRESS SEMICONDUCTOR Features Cache Controller and Memory Management Unit Fully conforms to the SPARC refer­ ence M emory M anagement Unit M M U architecture

IBM processor

Abstract: ibm technical IBM3206K0424 RISCwatch SCR Handbook, rca
Contextual Info: â IBM Processor for Network Resources Revision 2.5 Databook Preliminary â Copyright and Disclaimer  Copyright International Business Machines Corporation 1999 All Rights Reserved Printed in the United States of America August 1999 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.

IBM processor

Abstract: RISCwatch IBM powerpc 405 walnut
Contextual Info:  IBM Processor for Network Resources Revision 2.5 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America August 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.

Tlb8

Abstract: mips r2000a R2000A R2000 mips Siemens R2000 Q67120-C552 R3000 SAB-R2000A SAB-R2000 SAB-R2000A-16-A
Contextual Info: SIEMENS High Performance 32-Bit RISC Microprocessor SAB-R2000A Including on-chip memory management and cache control with support for up to three external coprocessors including the SAB-R2010A floating point accelerator. Advance Information • On-chip memory management unit

IBM powerpc 405 walnut

Abstract: RX TSOP 1738 SCR BRX 49 PIN IBM processor IBM3206K0424 65z5 RISCwatch BIOS Flash ROM Chip
Contextual Info:  IBM Processor for Network Resources Revision 2.5 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America August 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.

Contextual Info:  IBM Processor for Network Resources Version 2.61 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America May 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries,

IBM32NPCXX1EPABBE66

Abstract: IBM processor of relay RAS 0510 DC RISCwatch
Contextual Info:  IBM Processor for Network Resources Version 2.61 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America July 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries,

RISCwatch

Abstract: ppc jtag
Contextual Info:  IBM Power Network Processor, Resource Manager NPr2.7 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America July 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries,

nrm 3811 as

Abstract: IBM processor RISCwatch X3401 X0203
Contextual Info:  IBM Processor for Network Resources Version 2.61 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America July 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries,