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    VHDL CODE SWITCH LAYER 2 Search Results

    VHDL CODE SWITCH LAYER 2 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TCWA1225G
    		Toshiba Electronic Devices & Storage Corporation High Power Switch / SPDT / WCSP14 Datasheet
    BAV99
    		Toshiba Electronic Devices & Storage Corporation Switching Diode, 100 V, 0.215 A, SOT23 Datasheet
    1SS403E
    		Toshiba Electronic Devices & Storage Corporation Switching Diode, 200 V, 0.1 A, ESC Datasheet
    TBAV70
    		Toshiba Electronic Devices & Storage Corporation Switching Diode, 80 V, 0.215 A, SOT23 Datasheet
    TBAS16
    		Toshiba Electronic Devices & Storage Corporation Switching Diode, 80 V, 0.215 A, SOT23 Datasheet

    VHDL CODE SWITCH LAYER 2 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CRC-10

    Abstract: LUC4AB01 LUC4AU01 vhdl code switch layer 2 8 bit microprocessor using vhdl vhdl code layer 2 switch orca vhdl code for 555
    Contextual Info: Product Brief August 2000 ATM ABR Cell Manager/Processor CSC for ORCA FPGAs Features • ■ Complete available bit rate ABR service solution when used with the Lucent Technologies Atlanta ATM chipset Implements Lucent Bell Labs dynamic max rate algorithm (DMRCA) for ABR


    Original     		PB00-091NCIP CRC-10 LUC4AB01 LUC4AU01 vhdl code switch layer 2 8 bit microprocessor using vhdl vhdl code layer 2 switch orca vhdl code for 555 PDF

    vhdl code for deserializer

    Abstract: vhdl code for parallel to serial converter vhdl code for rs232 receiver free vhdl code for pll vhdl code for phase frequency detector vhdl code for clock and data recovery CY7B923 CY7B933 CY7C451 DC-202
    Contextual Info: Serializing High-Speed Parallel Buses to Extend Their Operational Length Introduction Switch Parallel buses are used in many designs for the purpose of moving data from one point to another. VMEbus, ISA, EISA, VESA, PCI, SBus, and NuBus are some of the more familiar


    Original     		PDF

    vhdl code switch layer 2

    Abstract: vhdl code for asynchronous fifo
    Contextual Info: UTOPIA Slave CC143S January 10, 2000 C ooreEl MicroSystems CoreEl MicroSystems 46750 Fremont Blvd. #208 Fremont, CA 94538 USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 URL: www.coreel.com E-mail: sales@coreel.com Features • Supports 4000X, Spartan -II, Virtex™, and Virtex™-E


    Original     		CC143S) 4000X, 8/16-bit 32-bit CC143S vhdl code switch layer 2 vhdl code for asynchronous fifo PDF

    vhdl code for 8 bit ODD parity generator

    Abstract: vhdl code for 8-bit calculator vhdl code for 4 bit even parity generator vhdl code for 8 bit parity generator XC4013XL PIN BG256 vhdl code for 8-bit parity generator XC4000XL
    Contextual Info: UTOPIA Master CC140f March 23, 1998 Product Specification C ooreEl AllianceCORE Facts MicroSystems CoreEl Microsystems 46750, Fremont Blvd.Suite 208 Fremont, CA -94538 USA. Phone: +1 510-770-2277 Fax: +1 510-770-2288 Email: sales@coreel.com URL: www.coreel.com


    Original     		CC140f) vhdl code for 8 bit ODD parity generator vhdl code for 8-bit calculator vhdl code for 4 bit even parity generator vhdl code for 8 bit parity generator XC4013XL PIN BG256 vhdl code for 8-bit parity generator XC4000XL PDF

    vhdl code for 8-bit calculator

    Abstract: vhdl ODD parity generator XC4013XL PIN BG256 vhdl code for 8 bit ODD parity generator XC4000XL vhdl code for 4 bit even parity generator
    Contextual Info: UTOPIA Master CC140f March 23, 1998 Product Specification C ooreEl AllianceCORE Facts MicroSystems CoreEl Microsystems 4046 Clipper Court Fremont, CA -94538 USA. Phone: +1 510-770-2277 Fax: +1 510-770-2288 Email: sales@coreel.com URL: www.coreel.com Features


    Original     		CC140f) vhdl code for 8-bit calculator vhdl ODD parity generator XC4013XL PIN BG256 vhdl code for 8 bit ODD parity generator XC4000XL vhdl code for 4 bit even parity generator PDF

    vhdl code for mac transmitter

    Abstract: verilog code CRC generated ethernet packet XIP2177 XIP2178 CRC SOURCE CODE IN VHDL Cyclic Redundancy Check simulation IMPLEMENTATION OF IEEE 802.3 MAC TRANSMITTER USING VHDL
    Contextual Info: CoreEl 10Gb Ethernet MAC CC410 May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com Features


    Original     		CC410) OC-192c vhdl code for mac transmitter verilog code CRC generated ethernet packet XIP2177 XIP2178 CRC SOURCE CODE IN VHDL Cyclic Redundancy Check simulation IMPLEMENTATION OF IEEE 802.3 MAC TRANSMITTER USING VHDL PDF

    cell phone

    Abstract: CC-14-1 vhdl code 8 bit processor BG256 CRC-10 CRC-32 XC4000XL
    Contextual Info: UTOPIA Slave CC-141 January 26, 1998 C ooreEl MicroSystems CoreEl MicroSystems 46750 Fremont Blvd. #208 Fremont, CA 94538 USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 URL: www.coreel.com E-mail: sales@coreel.com Features • • • • • • • •


    Original     		CC-141) cell phone CC-14-1 vhdl code 8 bit processor BG256 CRC-10 CRC-32 XC4000XL PDF

    vhdl code for 9 bit parity generator

    Abstract: asynchronous fifo vhdl xilinx XAPP263 vhdl code for fifo and transmitter vhdl code for lvds driver vhdl code for phase shift X263 full vhdl code for input output port verilog code for transmission line vhdl code switch layer 2
    Contextual Info: Application Note: Virtex-II and Virtex-II Pro Series R XAPP263 v1.1 December 19, 2005 Summary Virtex-II SelectLink Communications Channel Author: John Logue Systems with two or more FPGAs often require high-bandwidth datapaths between devices. As the clock period and switching times of digital circuits become shorter, straightforward methods


    Original     		XAPP263 X111Y36; X111Y35; X111Y33; X111Y32; X111Y31; X111Y29; X111Y28; X111Y27; X111Y23; vhdl code for 9 bit parity generator asynchronous fifo vhdl xilinx XAPP263 vhdl code for fifo and transmitter vhdl code for lvds driver vhdl code for phase shift X263 full vhdl code for input output port verilog code for transmission line vhdl code switch layer 2 PDF

    X26302

    Abstract: vhdl code for 9 bit parity generator XAPP263 asynchronous fifo vhdl vhdl code for fifo and transmitter XC2V1000-FG456 VHDL Bidirectional Bus Signal Path Designer
    Contextual Info: Application Note: Virtex-II and Virtex-II Pro Series R XAPP263 v1.0 July 16, 2002 Summary Virtex-II SelectLink Communications Channel Author: John Logue Systems with two or more FPGAs often require high-bandwidth data paths between devices. As the clock period and switching times of digital circuits become shorter, straightforward


    Original     		XAPP263 X111Y36; X111Y35; X111Y33; X111Y32; X111Y31; X111Y29; X111Y28; X111Y27; X111Y23; X26302 vhdl code for 9 bit parity generator XAPP263 asynchronous fifo vhdl vhdl code for fifo and transmitter XC2V1000-FG456 VHDL Bidirectional Bus Signal Path Designer PDF

    vhdl code for pci express

    Abstract: verilog code for pci express memory transaction plx vhdl code NVIDIA nForce verilog code for pci express nFORCE NVIDIA nForce 4 SE7525RP2 interrupt vhdl vhdl code for gold code
    Contextual Info: PCI Express Compiler Data Sheet June 2005, Ver. 1.0 Introduction The PCI Express Compiler generates customized PCI Express MegaCore functions that you can use to design PCI Express endpoints, including nontransparent bridges, or unique designs combining multiple PCI Express components in a single Altera® device. The PCI Express


    Original     		PDF

    CC-401

    Abstract: XIP209 XIP210 verilog code for spi4.2 interface
    Contextual Info: CoreEl SPI-4 Phase 2 Interface Core CC401 May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com


    Original     		CC401) OIF-SPI402 OC-192, CC401 CC410 CC-401 XIP209 XIP210 verilog code for spi4.2 interface PDF

    traffic light controller IN JAVA

    Abstract: vhdl code for traffic light control verilog hdl code for parity generator sdc 2025 altera CORDIC ip error correction code in vhdl interlaken Reed-Solomon Decoder verilog code verilog code for fir filter modelsim 6.3g
    Contextual Info: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: 10.0 Document Version: 10.0.2 Document Date: 15 September 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    ERC32

    Abstract: leon TSC695 Evaluation Kit TSC695
    Contextual Info: TSC695 Evaluation Kit . Getting Started Guide -2 7831A–AERO–04/09 TSC695 Evaluation Kit - Getting Started Guide -4 7831A–AERO–04/09 TSC695 Evaluation Kit - Getting Started Guide


    Original     		TSC695 ERC32 leon TSC695 Evaluation Kit PDF

    vhdl code switch layer 2

    Contextual Info: POS-PHY Level 2 MegaCore Function December 2000 User Guide Version 1.0 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-PL2-1.0 POS-PHY Level 2 MegaCore Function User Guide Altera, ACEX, APEX, APEX 20K, FLEX, FLEX 10KE, MAX+PLUS II, MegaCore, MegaWizard, OpenCore, and Quartus are


    Original     		PDF

    K2811

    Abstract: p22bc XAPP336 XAPP391
    Contextual Info: Application Note: CoolRunner R XAPP336 v1.3 January 15, 2003 Design of a 16b/20b Encoder/Decoder Using a CoolRunner XPLA3 CPLD Summary This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx CoolRunner XPLA3 CPLD. CoolRunner CPLDs are the


    Original     		XAPP336 16b/20b 8b/10b K2811 p22bc XAPP336 XAPP391 PDF

    Marvell PHY 88E1111 Datasheet

    Abstract: 88E1111 88E1111 PHY registers map 88E1145 Marvell 88E1111 Transceiver Marvell PHY 88E1111 stratix iii Datasheet vhdl code for ddr2 vhdl median filter programming 88E1111 vhdl code for FFT 32 point
    Contextual Info: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: Document Version: Document Date: 9.0 9.0.5 1 July 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    COOLRUNNER-II examples

    Abstract: error detection code in vhdl XAPP336 XAPP391 XC2C128-6VQ100 vhdl code switch layer 2
    Contextual Info: Application Note: CoolRunner-II CPLD R XAPP391 v1.0 January 15, 2003 Design of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD Summary This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx CoolRunner -II CPLD. CoolRunner CPLDs are the lowest


    Original     		XAPP391 16b/20b 8b/10b COOLRUNNER-II examples error detection code in vhdl XAPP336 XAPP391 XC2C128-6VQ100 vhdl code switch layer 2 PDF

    CTXIL206

    Abstract: vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS
    Contextual Info: Audio/Video Connectivity Solutions for Spartan-3E FPGAs Reference Designs for the Broadcast the Broadcast Industry: Volume 3 Industry: Volume 3 [optional] XAPP1015 v1.0 September 28, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		XAPP1015 CTXIL206 vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS PDF

    micron flash controller

    Abstract: SPI flash High speed EP1S60 EP1S60F1020C6 EPM3256A 0X1172 128X64 LCD vhdl code for lcd display PCI_T32 MegaCore pc atx power supply
    Contextual Info: PCI High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com P25-09629-00 Kit Version: 1.0.0 Document Version: 1.0.0 Document Date: September 2003 Copyright PCI High-Speed Development Kit, Stratix Professional Edition


    Original     		P25-09629-00 micron flash controller SPI flash High speed EP1S60 EP1S60F1020C6 EPM3256A 0X1172 128X64 LCD vhdl code for lcd display PCI_T32 MegaCore pc atx power supply PDF

    Marvell PHY 88E1111 Datasheet

    Abstract: 88E1145 88E1111 PHY registers map 88E1111 marvell ethernet switch sgmii verilog code for cordic algorithm using 8-fft SMPTE425M verilog code for CORDIC to generate sine wave scaler verilog code dc bfm
    Contextual Info: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: 8.1 Document Version: 8.1.3 Document Date: 1 February 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    EP20K30EFC324-1

    Abstract: EP20K30EQC208-1 IP-UTOPIA2MS
    Contextual Info: UTOPIA Level 2 Master MegaCore Function 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: Document Version: Document Date: 2.1.1 2.1.1 rev1 January 2003 UTOPIA Level 2 Master MegaCore Function User Guide Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all


    Original     		PDF

    VHDL CODE FOR HDLC controller

    Abstract: Multi-Channel hdlc Controller CRC16 hdlc ispMACH 4000 CRC-16 CRC32 CRC-32 CRC-16 and CRC-32 design of HDLC controller using vhdl
    Contextual Info: HDLC Controller Implemented in ispMACH 4000 and 5000VG Families November 2002 Reference Design RD1009 Introduction HDLC is the abbreviation for High-Level Data Link Control published by the International Standards Organization ISO . This data link protocol is located at the link layer (layer 2) of the 7-layer OSI reference model. Today, a variety


    Original     		ispMACHTM4000 5000VG RD1009 CRC-16 CRC-32 1-800-LATTICE VHDL CODE FOR HDLC controller Multi-Channel hdlc Controller CRC16 hdlc ispMACH 4000 CRC-16 CRC32 CRC-32 CRC-16 and CRC-32 design of HDLC controller using vhdl PDF

    mega pro remote

    Abstract: Ethernet-MAC using vhdl manchester verilog decoder 100BASE-FX MAC110 MSM38S0000 W110 W110M vhdl code for deserializer
    Contextual Info: W110 TB.fm NEw Page -1 Monday, August 12, 2002 5:46 PM TECHNICAL BRIEF O K I A S I C P R O D U C T S W110 100BASE-T + 10BASE-T Dual-Speed Ethernet MAC Mega Macrofunction July 1996 W110 TB.fm NEw Page 0 Monday, August 12, 2002 5:46 PM • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––


    Original     		100BASE-T 10BASE-T mega pro remote Ethernet-MAC using vhdl manchester verilog decoder 100BASE-FX MAC110 MSM38S0000 W110 W110M vhdl code for deserializer PDF

    CRC-16 and verilog

    Abstract: vhdl code scrambler CRC-16 CRC-32 OTN SWITCH header G.7041 GFP XC2V500-5 CRC-16 and CRC-32 Ethernet
    Contextual Info: CoreEl 8-Bit Multichannel GFP Framer CC225 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation CC225 Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		CC225) CC225 apCC225 CRC-16 and verilog vhdl code scrambler CRC-16 CRC-32 OTN SWITCH header G.7041 GFP XC2V500-5 CRC-16 and CRC-32 Ethernet PDF