VALID LOGIC SYSTEMS Search Results

AAAC

Contextual Info: April 2004 ASM4SSTVF16857 rev 1.1 DDR 14-Bit Registered Buffer LVCMOS level at a valid logic state since VREF may Features • not be stable during power-up. Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 To ensure that outputs are at a defined logic state

ASM4SSTVF16857

Abstract: 48TT ASM5CVF857 JC42 PC2100 PC2700 PC3200 marking AAAC
Contextual Info: August 2004 ASM4SSTVF16857 rev 2.0 DDR 14-Bit Registered Buffer LVCMOS level at a valid logic state since VREF may Features • not be stable during power-up. Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 To ensure that outputs are at a defined logic state

TAG A3

Abstract: burndy MODULE intel sram CYM7427PB-20 CYM7428PB-20
Contextual Info: CYM7427 CYM7428 ADVANCED INFORMATION 82420 PCIsetĆCompatible Level II Cache Module Family Features D D D D D D D D D Cache size 128 Kbytes or 256 Kbytes Tag width of 7 bits plus valid bit Independent dirty bit Operates with systems based on the Intel 82420 core logic

LVT16245

Contextual Info: Cover Story BUS TERMINATION Terminating buses in computer designs To maintain reliability in a typical computer system that is idle or being reconfigured, you must design system interconnects such that they maintain or transition to a valid logic level. You can use several

JC-42

Abstract: AAAC
Contextual Info: June 2004 ASM4SSTVF16857 rev 1.1 DDR 14-Bit Registered Buffer LVCMOS level at a valid logic state since VREF may Features • not be stable during power-up. Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 & PC3200.

Contextual Info: M-957 DTJIIIF Receiver *v detection of a valid end-of-signal pause or by the CLEAR input. An early signal presence indicator, BD, facilitates applications requiring tone blocking. The data outputs operate with simple logic circuits or microprocessors, and are threestate enabled to facilitate bus-oriented architectures.

400X

Abstract: 9301DMQB 9301FMQB C1995 DM9301 DM9301N J16A N16E W16A 9301DM
Contextual Info: 9301 DM9301 1-of-10 Decoders General Description Features These BCD-to-decimal decoders consist of eight inverters and ten 4-input NAND gates The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates Full decoding of valid input logic ensures that

957a

Abstract: 75T957A-1P Teltone M-957 75T957-IP qau3
Contextual Info: IIE SILICON SYSTEMS INC Mmsuskms 0 2 5 3 ^ 5 Qaü37?Q 1 • D SSI 75T957/957A DTMF Receiver with Diai Tone Reject Filtér — T -7 S -T 7 -0 7 May, 1989 FEATURES DESCRIPTION The SSI 75T957/957A combines swltched-capacitor and digital frequency measuring techniques to decode

Contextual Info: ICS1889 Integrated Circuit Systems, Inc. Product Preview 100Base-FX Integrated PHYceiver General Description Features The ICS1889 is a fully integrated physical layer device sup­ porting 100 Megabits per second CSMA/CD Fast Ethernet fiber optic applications. It is designed to support the require­

Contextual Info: Multiple FIFO Configuration in ispLSI 6192 Figure 1. ispLSI 6192 Functional Block Diagram Introduction In various data communications applications, it is often necessary to transmit and receive large blocks of data at high data rates between two systems. The size of the

MUX41

Abstract: DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT dbit53 "Single-Port RAM"
Contextual Info: Multiple FIFO Configuration in ispLSI 6192 Figure 1. ispLSI 6192 Functional Block Diagram Introduction In various data communications applications, it is often necessary to transmit and receive large blocks of data at high data rates between two systems. The size of the

22V10C

Abstract: ATF22LV10C-10JC ATF22LV10C ATF22LV10C-10PC ATF22LV10C-10SC ATF22LV10C-15JC ATF22LV10CZ ATF22V10C
Contextual Info: ATF22LV10C Features • • • • • • • • • • • • 3.0V to 3.6V Operating Range Advanced Low Voltage Electricaly Erasable Programmable Logic Device User Controlled Power Down Pin Option Pin-Controlled Standby Power 10 µA Typical Well-Suited for Battery Powered Systems

MUX41

Contextual Info: Multiple FIFO Configuration in ispLSI 6192 Figure 1. ispLSI 6192 Functional Block Diagram Introduction In various data communications applications, it is often necessary to transmit and receive large blocks of data at high data rates between two systems. The size of the

Contextual Info: Multiple FIFO Configuration in ispLSI 6192 Figure 1. ispLSI 6192 Functional Block Diagram Introduction In various data communications applications, it is often necessary to transmit and receive large blocks of data at high data rates between two systems. The size of the

Contextual Info: ülmËL Features • • • • • • • • • 3.0V to 5.5V Operating Range Advanced Low Voltage Electricaly Erasable Programmable Logic Device User Controlled Power Down Pin Option Pin-Controlled Standby Power 10 |iA Typical Well-Suited for Battery Powered Systems

22V10 ATMEL

Abstract: 22V10C ATF22LV10C ATF22LV10C-10JC ATF22LV10C-10PC ATF22LV10C-10SC ATF22LV10CZ ATF22V10C
Contextual Info: Features • • • • • • • • • • • • 3.0V to 5.5V Operating Range Advanced Low Voltage Electricaly Erasable Programmable Logic Device User Controlled Power Down Pin Option Pin-Controlled Standby Power 10 µA Typical Well-Suited for Battery Powered Systems

E84-0200A

Abstract: E-84
Contextual Info: Intel Corporation 5000 W. Chandler Blvd. Chandler, AZ 85226 Component Automation Systems Material Handling Systems E84 Memo Date: Subject: To: From: 19 May 2000 Clarification of Potential 300mm SEMI E84 Issues and Supplier Expectations All 300mm Equipment Supplier E84 Software Experts

AH8304TC

Abstract: AH8304TM 16 bit gray code to binary converter
Contextual Info: Description The AH8304 video D/A converters are third generation hybrid devices that provide designers of low- to mediumcost color display systems with a complete, self-contained, TTL com­ patible, composite video subsystem in a 24 pin DIP. Offered as both an

cm8870 dtmf decoder

Abstract: cm8870 dtmf decoder circuit diagram cm8870 DTMF 8888-2 CM8870 CM8888 CM8888-2 CM8870 applications
Contextual Info: CM8888/8888-2 CALIFORNIA MICRO DEVICES CMOS INTEGRATED DTMF TRANCEIVER Applications • Paging systems • Repeater systems/mobile radio • Interconnect dialers • PABX systems • Computer systems • Fax machines • Pay telephones • Credit card verification

HDAS-524MC

Abstract: HDAS-524MM HDAS-528MC RN55C
Contextual Info: HDAS-524, HDAS-528 ® 12-Bit, 400kHz, Complete Data Acquisition Systems INNOVATION and EXCELLENCE FEATURES • • • • • • 12-Bit resolution, 400kHz throughput 8 Channels single-ended or 4 channels differential Miniature, 40-pin, ceramic DDIP Full scale input range from 100mV to 10V

ICS1889

Abstract: ICS1890
Contextual Info: ICS1889 Integrated Circuit Systems, Inc. 100Base-FX Integrated PHYceiverTM General Description Features The ICS1889 is a fully integrated physical layer device supporting 100 Megabits per second CSMA/CD Fast Ethernet fiber optic applications. It is designed to support

Contextual Info: BACK ICS1889 Integrated Circuit Systems, Inc. 100Base-FX Integrated PHYceiverTM General Description Features The ICS1889 is a fully integrated physical layer device supporting 100 Megabits per second CSMA/CD Fast Ethernet fiber optic applications. It is designed to support

FAG 50 diode

Abstract: diode FAG 50 32-PIN QS32383 QS3383 FAG 28 diode
Contextual Info: QS7244A Q High-Speed High Speed CMOS 4K Bus x 9 Clocked FIFO Exchange Switches with Output Enable QS3383 QS7244A QS32383 FEATURES/BENEFITS • • • • • • Clocked interface FIFOs for high-speed systems Data and flags change on rising edge of clocks

CSSK

Contextual Info: SEMICONDUCTOR TM NM95MS15 Plug and Play Front-End Device for ISA-Bus Systems General Description Features The NM95MS15 is one of the family of single chip solutions designed to provide complete Plug and Play capability for ISA bus systems. The NM95MS15 includes the necessary state machine