ULTRA338020 Search Results
ULTRA338020 Datasheets (1)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
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Ultra338020 |
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UltraLogic Very High Speed 20K Gate 3.3V CMOS FPGA | Scan | 102.45KB | 1 |
ULTRA338020 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: 7c338020: Wednesday, September 6, 1995 Revision: October 25, 1995 ADVANCED INFORMATION UltraLogict Very High Speed 20K Gate 3.3V CMOS FPGA Features D Full 3.3V operation D Very high speed D D D D D D Ultra338020 D Ċ Loadable counter frequencies greater than 100 MHz |
Original |
7c338020: Ultra338020 208pin 352pin Ultra38000t Ultra38000 7C3380201 Ultra3800, | |
Contextual Info: ADVANCED INFORMATION 5f CYPRESS UltraLogic Very High Speed 20K Gate 3.3V CMOS FPGA — Very low cell propagation delay 1.4 ns typical Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies |
OCR Scan |
208-pin 352-pin 16-bit 00BBBBBBBBEEEÂ 3000000BBBBB000000 0BBBBBBB0BB000BBBBBBBBFÂ 3H00B0000BBBEEH00B 1B0B000000BBHHHH0E1 000000EE00BBBB0B00 BE00BE0BBB00B000BE | |
Contextual Info: y CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • U nparalleled FPGA performance for counters, data path, state machines, |
OCR Scan |
Ultra338020 ltra38000, | |
ALI chipset Ali 3516
Abstract: SEM 2006 6216 static ram sem 2005 ALI chipset Ali 3510 vl82c483 ali 3516 CMOS 5408 PAL Decoder 16L8 1K x 8 static ram
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Original |
CY101E383 CY10E383 CY2071 CY2081 CY2250 CY2252 CY2254A CY2255 CY2257 CY2260 ALI chipset Ali 3516 SEM 2006 6216 static ram sem 2005 ALI chipset Ali 3510 vl82c483 ali 3516 CMOS 5408 PAL Decoder 16L8 1K x 8 static ram | |
Contextual Info: > CYPRESS Features • Full 33V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines, |
OCR Scan |
208-pin 352-pin 16-bit SIC380 pASIC380, |