U 74 HCT 74 Search Results
U 74 HCT 74 Result Highlights (1)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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SN74HCT04PWRG4 |
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HCT SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, TSSOP-14 |
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U 74 HCT 74 Price and Stock
Nexperia 74HCT125D,653Buffers & Line Drivers SOT108-1 BUFFERS & LINE DVRS |
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74HCT125D,653 | 30,953 |
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Nexperia 74HCT00D,653Logic Gates SOT108-1 QUAD 2-INPUT NAND |
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74HCT00D,653 | 9,115 |
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Nexperia 74HCT123D,653Monostable Multivibrator SOT109-1 MONOSTABLE MULTIVBTR |
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74HCT123D,653 | 5,781 |
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Nexperia 74HCT4053D,118Multiplexer Switch ICs SOT109-1 MLTI/DEMULT TRPL 2CH |
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74HCT4053D,118 | 4,947 |
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Nexperia 74HCT257D,653Encoders, Decoders, Multiplexers & Demultiplexers SOT109-1 QUAD 2INPUT MULTPLXR |
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74HCT257D,653 | 3,387 |
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U 74 HCT 74 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: GD54/74HC374, GD54/74HCT374 OCTAL 3-STATE NONINVERTING D-TYPE FLIP-FLOPS General Description Pin Configuration These devices are identical in pinout to the 5 4 /7 4 L S 3 7 4 . T hey co n ta in e ig h t D -type master/slave flip-flops with a common clock and |
OCR Scan |
GD54/74HC374, GD54/74HCT374 | |
Contextual Info: 7 4 H C /H C T 74 flip-flops D U A L D -TYPE FLIP-FLO P W IT H SET A N D RESET; PO SITIVE -E D G E T R IG G E R FEATURES • • TYPICAL Output capability : standard IcC category: flip-flops SYMBOL The 74HC/HCT74 are dual positiveedge triggered, D-type flip-flops with |
OCR Scan |
74HC/HCT74 | |
Cmos 74 HC
Abstract: 74HC HCT366 hct 367 it94 t46a
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GD54/74HC366, GD54/74HCT366 54/74LS366. GD74HCT366 GD54HCT366 402A757 Cmos 74 HC 74HC HCT366 hct 367 it94 t46a | |
ic 74 hc 10Contextual Info: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 4 . They consist of two D-type flip-flops with individual preset, clear, and clock inputs. Infor mation at a D-input is transferred to the correspon |
OCR Scan |
GD54/74HC74, GD54/74HCT74 ic 74 hc 10 | |
74HC541
Abstract: C074H 74HCT541
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CD54/74HC540, CD54/74HCT540 CD54/74HC541, CD54/74HCT541 CD54/74HC540 CD54/74HC541 CD54/74HCT541 5I30R3 CD54/74HC, 74HC541 C074H 74HCT541 | |
74HC74
Abstract: 74ls74 timing setup hold 74hc74 pin diagram 74LS74 PINOUT 74HC74 pin configuration 74hct74 Current 74HCT74 TTL 74hc74 74HC GD74HCT74
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OCR Scan |
GD54/74HC74, GD54/74HCT74 54/74LS74. 74HC74 74ls74 timing setup hold 74hc74 pin diagram 74LS74 PINOUT 74HC74 pin configuration 74hct74 Current 74HCT74 TTL 74hc74 74HC GD74HCT74 | |
74HCT family spec
Abstract: 74HCT541LC 74hct 347 74HCT541D 74HCT541P 54HCT540D 54HCT541D 74HCT 74HCT540D 74HCT540P
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HCT540 HCT541 74HCT 54HCT 20-pin 74HCT540P 74HCT541P 74HCT540D 74HCT541D 74HCT family spec 74HCT541LC 74hct 347 54HCT540D 54HCT541D | |
Contextual Info: Technical Data CD54/74HC4020 CD54/74HCT4020 File Number 1484 High-Speed CMOS Logic 14-Stage Binary Counter Type Features: • • ■ ■ ■ MÄSTt» ftESET Fully static operation Buttered inputs Common reset Negative edge pulsing Typical fM*x = 50 MHz @ VCc = 5 V, Cl = 15, T* = 25° C |
OCR Scan |
CD54/74HC4020 CD54/74HCT4020 14-Stage RCA-CD54/74HC4020 14stage CD54HC4020 CD54HCT4020 16lead | |
HCT74
Abstract: lz93 100 pin 74HC 74HCT
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OCR Scan |
74HC/HCT74 7110fleb HCT74 lz93 100 pin 74HC 74HCT | |
Contextual Info: 74HC/HCT00 SSI QUAD 2-INPUT N AND GATE FEATURES TYPIC AL • Output capability: standard • UN IT CONDITIONS PARAMETER SYM BOL l CC cate gory: SSI The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible w ith low power S chottky T T L LSTTL . They are specified in |
OCR Scan |
74HC/HCT00 74HCT | |
Cmos 74 HC4060
Abstract: HC393 HC590 LS192 HC4060 HC390 HC4022 HC4520 4518B 4 bit binary divider
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OCR Scan |
M54/74 HC161 HCT161 HC162 HC190 HC191 HC192 HC193 HC292 HC294 Cmos 74 HC4060 HC393 HC590 LS192 HC4060 HC390 HC4022 HC4520 4518B 4 bit binary divider | |
PC 74 HCT 32 P
Abstract: 74HCT541 x0e1 74hct541t 74HC541 74HCT541M
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OCR Scan |
CD54/74HC540, CD54/74HCT540 CD54/74HC541, CD54/74H 54/74HCT 92CS-35I30R3 CD54/74HC, HCT540 HCT541 PC 74 HCT 32 P 74HCT541 x0e1 74hct541t 74HC541 74HCT541M | |
74HCT541Contextual Info: _ File Number CD54/74HC540, CD54/74HCT540 CD54/74HC541, CD54/74HCT541 1659 57E D HARRIS SEMICOND SECTOR • M302571 GQ17Ô3L □ S3 HAS "P52r0l High-Speed CMOS Logic AO— - "-Y O A 1 -1 ^ -Y 1 IS —Y2 < - 4 TCO a* ¿Ü _Y3 A4- A Já-Y4 |
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CD54/74HC540, CD54/74HCT540 CD54/74HC541, CD54/74HCT541 M302571 P52r0l CD74HCIHC 54/74HC 54/74HCT 92CS-35I30R3 74HCT541 | |
Contextual Info: 7 4 H C /H C T 04 SSI H E X IN V E R T E R - FEATURES T Y P IC A L • O u tp u t c a p a b ility : sta n d a rd • Ic C cate9o r Y- SSI G E N E R A L D E S C R IP T IO N The 74H C /H C T 04 are high-speed Si-gate CMOS devices and are pin com patible w ith lo w pow er S c h o ttk y |
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74HC74
Abstract: 74hct74 74LS74 pinout 74HC74 pin configuration 74hc74 pin diagram TTL 74hc74 74ls74 timing setup hold Current 74HCT74 QQ042 000M2AA
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OCR Scan |
GD54/74HC74, GD54/74HCT74 54/74LS74. 00042T1 402A757 DQ042T2 74HC74 74hct74 74LS74 pinout 74HC74 pin configuration 74hc74 pin diagram TTL 74hc74 74ls74 timing setup hold Current 74HCT74 QQ042 000M2AA | |
74HCT374
Abstract: 74HC374 74HC GD74HC374
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OCR Scan |
GD54/74HC374, GD54/74HCT374 54/74LS374. 74HCT374 74HC374 74HC GD74HC374 | |
GD74HC174
Abstract: 74HC
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OCR Scan |
GD54/74HC174, GD54/74HCT174 54/74LS1 GD74HC174 74HC | |
Contextual Info: Technical Data CD54/74HC4020 CD54/74HCT4020 File N um ber 1484 High-Speed CMOS Logic 14-Stage Binary Counter Type Features: • ■ ■ • ■ MASTER RESET F u lly sta tic operatio n B uffe red inpu ts C om m on reset N egative edge p u ls in g Typical f M* x = 50 MHz @ VCc = 5 V, CL = 15, 7 * = 25° C |
OCR Scan |
CD54/74HC4020 CD54/74HCT4020 14-Stage RCA-CD54/74HC4020 CD54/74HCT4020 14stage CD54HC4020 CD54HCT74HCT 54HCT CD54/74H | |
74xxx
Abstract: philips cmos burn-in
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OCR Scan |
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IC 7458
Abstract: 7458 rca ic 7458 ic
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OCR Scan |
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4 bit magnitude comparator
Abstract: 74HC 74HCT S020 VM 688
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OCR Scan |
74HC/HCT688 7ZB799Â 4 bit magnitude comparator 74HC 74HCT S020 VM 688 | |
Contextual Info: 7 4 H C /H C T 73 flip-flops D U A L JK FLIP-FLO P W IT H RESET; N E G A T IV E -E D G E T R IG G E R FEATURES T Y P IC A L • Output capability: standard • ICC category; fJip-fJops The 74H C /H C T 73 are dual negativeedge triggered JK-type flip-flops _ |
OCR Scan |
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Contextual Info: Technical Data p ile N um ber CD54/74HC540, CD54/74HCT540 CD54/74HC541, CD54/74HCT541 1659 High-Speed CMOS Logic AO— — i5 - v o A1— 1 —— A 2 - — ——— Y2 A 3 — 5- ^ -Y 3 A 4 - - Y1 Y4 AS — — i¿ - Y S A6 — — - I " - Y8 A7— i |
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CD54/74HC540, CD54/74HCT540 CD54/74HC541, CD54/74HCT541 -CD54/74HC540 CD54/74HCT540 CD54/74HC, HCTS40 CDS4/74HC, HCT541 | |
CD74HC4020
Abstract: CD54HC4020 CD54HCT4020 CD74HCT4020 74HC4020 T45-2
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OCR Scan |
CD54/74HC4020 CD54/74H CT4020 43G2271 14-Stage RCA-CD54/74HC4020 CD54/74HCT4020 CD54HC4020 CD54HCT4020Transition CD74HC4020 CD54HCT4020 CD74HCT4020 74HC4020 T45-2 |