TXDATA13 Search Results

IDT77V1264L200

Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for

SA1381

Abstract: SS823 RDATA13 3RA61 AC21T n25h VSS1490 bwd9 HAD44 HAD48
Contextual Info: A B C D REVISIONS ZONE LTR CN8237/CX29704 PCB:BT01-D255-011 A DESCRIPTION INITIAL APPROVED DATE RELEASE 1 1 DL1 DELAYLINE 2.5NS 1 2 U7 3 CN8237 SEGMENTATION SCLK0 R124 18 DL2 B3SCLK0 A3SCLK1 R116 18 DELAYLINE 2.5NS POWER VDD PINS E7, E8, E11, E12, E15, E16

ht12 decoder

Abstract: 417-183 epd driver ic nec CB-11
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

93CS56L

Abstract: con20a 34.368Mhz oscillator TXDATA15 13k g4 TXDATA13 LA10 LA12 GPIO03 LA-1105
Contextual Info: 1 2 3 C15 0.1uF AD1 AD5 AD3 AD8 AD7 AD12 AD10 -CBE1 AD14 -SERR -LOCK -PERR CON1 1 CON1 J5 1 CON1 J4 1 CON1 J3 1 J2 -DEVSEL -IRDY AD17 -CBE2 AD21 AD19 -CBE3 AD23 AD27 AD25 AD31 AD29 CLK A C16 0.1uF C17 0.1uF C12 0.1uF VIO VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3

ATM25

Abstract: IDT77V1264L200 ST6200T
Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for

RX 433

Contextual Info: IDT77V1254L25 Quad Port PHY Physical Layer for 25.6 and 51.2 ATM Networks Features List ! ! ! ! ! ! ! ! ! ! ! ! Description Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 25.6 Mbps ATM channels

I960CA

Abstract: CN8236 CX28250EVM Bt8223
Contextual Info: CN8236 ATM ServiceSAR Plus with xBR Traffic Management The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface with service-specific functions in a single package for AAL0, 3/4, and 5 operations.

ic 313

Abstract: S3043 S3044
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98414 2.4 Gbps ATM SONET FRAMER The µPD98414 NEASCOT-P70 is one of ATM LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function for mapping an ATM cell passed from a high-end ATM layer

CBD10

Abstract: intel 7882 MARKING 09F PHAST-12E TXC-05802B TXC-05810 TXC-06212 SA 6356
Contextual Info: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 DESCRIPTION • 622 Mbit/s performance • UTOPIA Level 1/2 interface 8/16-bit with support for 64 ports • Tandem operation for two devices, supporting dual CellBus cell switching in load sharing or

HTD12

Abstract: 45x45 bga CBD62 cba8 373 ic HTD24 application of microprocessor in aircrafts 6-pin plastic A6 tray 45x45 CBD43
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT
PD98410 1.2G ATM SWITCH LSI DESCRIPTION The
PD98410 NEASCOT-X10TM is an LSI integrating ATM switch functions on a single chip. It has four UTOPIA level2 interfaces and can switch 24
24 circuits by using a multi-PHY connection. This LSI also realizes a switching

t04 68 3 pin transistor

Abstract: MD 202 flame relay AC03 nec alps lcd 14 pin t04 68 3 pin diode transistor z5t S3043 S3044 STM-16 z046
Contextual Info: User’s Manual µPD98414 NEASCOT-P70TM ATM 2.4Gbps SONET Framer Document No. S14166EJ4V0UM00 (4th edition) Date Published December 2001 J CP(K) 1999 1991 Printed in Japan [MEMO] 2 User's Manual S14166EJ4V0UM SUMMARY OF CONTENTS CHAPTER 1 GENERAL .13

8032 Intel Microprocessor data Sheet

Abstract: atm header error checking ATM machine using microcontroller dmo 265 NAIS 210 T7296 3-bit comparator circuit receives two 3-bit 8052 microcontroller Intel LOG RX 2 1018 IC ordinary calculator programming
Contextual Info: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public

DSLAM configuration AWS

Abstract: rx bc nbk TSC 13003 pcr 465 ATML 18751 circuit BKC International mpc82 bsdl nd1 marking code acm 33221
Contextual Info: MC92520 ATM Cell Processor User’s Manual MC92520UM/D Rev. 0, 12/2000 DigitalDNA and Mfax are trademarks of Motorola, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate Motorola integrated circuits or integrated

CN8237EBGB

Abstract: CX29704 RS8234 RS8235 PCI x1 express PCB dimensions artwork BC 5473
Contextual Info: CN8237 ATM OC-12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly ServiceSAR Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR

A01H

Abstract: 9FF MARKING T-RA18 SA 6356
Contextual Info: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 DESCRIPTION • 622 Mbit/s performance • UTOPIA Level 1/2 interface 8/16-bit with support for 64 ports • Tandem operation for two devices, supporting dual CellBus cell switching in load sharing or

Contextual Info: CUBIT-622 Device DATA SHEET PRODUCT PREVIEW DESCRIPTION FEATURES The CUBIT-622 device is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are built from a number of CUBIT-3,

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit September 1999-2 FEATURES l Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51.84Mbps) Applications l l Transmit Interface Characteristics l Accepts Either Single Rail or Dual Rail Data

Contextual Info: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2000 REV. 1.0.7 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.

NEC AC08

Abstract: S3043 S3044
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98414 2.4 Gbps ATM SONET FRAMER The µPD98414 NEASCOT-P70 is one of ATM LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function for mapping an ATM cell passed from a high-end ATM layer

TXC-05804-MB

Abstract: sot marking code w17 W17 marking code sot 23
Contextual Info: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET CUBIT®-Pro The CUBIT-3™ is a single-chip VLSI solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are constructed from a number of CellBus devices, all

7 segment display LTS 542

Abstract: lts 543 pin configuration lts 543 data sheet LTS 543 7 segment display 10 pin LTS 543 transmitter circuit in GPR lts 543 series pin diagram lts 542 pin diagram mips16 instruction set lts 543 pin diagram
Contextual Info: Preliminary User’s Manual VR4121 64/32-bit Microprocessor µPD30121 Document No. U13569EJ1V0UM00 1st edition Date Published August 1998 N CP(K) Printed in Japan [MEMO] 2 VR3000, VR4000, VR4100, VR4102, VR4111, VR4120, VR4121, VR4300, VR4305, VR4310, VR4400, VR5000,

PCI x1 express PCB dimensions artwork

Abstract: 140288 CN8237EBGB CN8236 RS8234 RS8235 RS8254
Contextual Info: CN8237 ATM OC12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly ServiceSAR Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR

nrzi clock recovery

Abstract: 77V1254 IDT77V1254 P3TC SF1153
Contextual Info: Quad Port PHY Physical Layer for 25.6 and 51.2 Mbps ATM Networks PRELIMINARY IDT77V1254 Integrated Device Technology, Inc. FEATURES DESCRIPTION • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 25.6 Mbps ATM channels