TTL REGISTER FILE Search Results

Contextual Info: SN74LS670 4 x 4 Register File with 3−State Outputs The TTL/MSI SN74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

74LS170

Abstract: 74LS670 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS170 4 x 4 REGISTER FILE OPEN-COLLECTOR The TTL / MSI SN54 / 74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

SN74LS670

Abstract: SN74LS670D SN74LS670DR2 SN74LS670N
Contextual Info: SN74LS670 4 x 4 Register File with 3-State Outputs The TTL/MSI SN74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

SN74LS670

Abstract: SN74LS670D SN74LS670N
Contextual Info: SN74LS670 4 x 4 Register File with 3-State Outputs The TTL / MSI SN74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

74LS170

Abstract: 74LS670 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS670 4 x 4 REGISTER FILE WITH 3-STATE OUTPUTS The TTL / MSI SN54 / 74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

motorola 74LS670

Abstract: Dip 28 motorola 74LS170 74LS670 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS670 4 x 4 REGISTER FILE WITH 3-STATE OUTPUTS The TTL / MSI SN54 / 74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

Fairchild 100K series ECL

Contextual Info: 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined

Contextual Info: ses 4 x 4 REGISTER FILE WITH 3-STATE OUTPUTS D E S C R IP T IO N The TTL/MSIT54LS670/T74LS670 is a high speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read

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Contextual Info: COM’L PAL16RA8 Advanced Micro Devices 20-pin Asynchronous TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 30 ns maxim um propagation delay and 20 MHz TTL-level register preload for testability f MAX Easy design w ith PA LA SM software ■

Contextual Info: M m o t o r o l a . SN54/74LS170 4 x 4 REGISTER FILE OPEN-COLLECTOR The TTL/MSI SN54/74LS170 is a high-speed, iow-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

Contextual Info: COM’L PAL16RA8 20-pin Asynchronous TTL Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • TTL-level register preload fo r testability 30 ns maxim um propagation delay and 20 MHz fM A X ■ Easy design with PA LA SM softw are

CD74AC164

Abstract: AC164 CD74AC164E CD74AC164M CD74ACT164 CD74ACT164E CD74ACT164M
Contextual Info: [ /Title CD74 AC164 , CD74 ACT16 4 /Subject (8Bit SerialIn/ParallelOut Shift Register) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan ced TTL) /Creator () CD74AC164, CD74ACT164 Data sheet acquired from Harris Semiconductor

SN74LS870

Contextual Info: TTL M SI TYPES SN54LS670, SN74LS670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS BU LLE TIN NO. D l-S 7612122, MARCH 1974-R EV 1SEO OCTOBER 1976 SNB4LS670 . . . J O R W PACKAGE • Separate Read/Write Addressing Permits

Contextual Info: INTEGRATED CIRCUITS - TTL TRANSISTOR TRANSISTOR LOGIC NTE74166, 16-Lead DIP, See Diag. 249 NTE74LS166 8-Bit Parallel or Serial-ln/Serial-Out Shift Register NTE74LS168A 16-Lead DIP, See Diag. 249 Synchronous Presettable BCD Decade Up/Down Counter NTE74LS169A

SN54170

Abstract: SN54170J SN74170 SN74170J
Contextual Info: CIRCUIT TYPES SN54170, SN74170 4-B Y-4 REGISTER FILES TTL MSI JOR N DUAL-IN-LINE OR W FLAT PACKAGE TOP VIEW '*’ • Separate Read/Write Addressing Permits Simultaneous Reading and Writing • Fast Access Times . . . Typically 20 ns • Open-Collector Outputs with 30-fiA

DI-74

Abstract: 2011AN2C
Contextual Info: www.fairchildsemi.com TMC2011A/2111A Variable-Length Shift Register Features Applications • Low power CMOS • TMC2011A is a pin compatible replacement for the TDC1011 and TMC2011 • TMC2211A is a pin compatible replacement for the TMC2111 • Inputs and outputs are TTL compatible

Contextual Info: PRELIM IN ARY COM’L a Advanced Micro Devices PALCE20RA1 OH-15 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ Programmable replacement for high-speed CMOS o rT TL logic TTL-level register preload for testability

Contextual Info: COM’L: H-15 ZI Advanced Micro Devices PALCE20RA1 OH-15 24-pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • ■ Programmable replacement for high-speed CMOS orTTL logic TTL-level register preload for testability Easy design with PALASM software

AR2425

Abstract: PD3024 PALCE20RA10
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 Lattice Semiconductor PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 100 mA ICC ■ TTL-level register preload for testability

AR2425

Abstract: PALCE20RA10 PD3024
Contextual Info: FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 100 mA ICC ■ TTL-level register preload for testability ■ As fast as 7.5 ns maximum propagation delay

Contextual Info: FIN A L COM’L: H-7/10/15/20 IND: H-7/10/15/20 Lattice/Vantis PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • TTL-level register preload for testability Low power at 100 mA Icc Extensive third-party software and programmer

Contextual Info: IND: H-7/10/15/20 COM’L: H-7/10/15/20 Advanced Micro Devices PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 100 mA Icc ■ TTL-level register preload for testability ■ As fast as 7.5 ns maximum propagation delay

AR2425

Abstract: palce20ra10 Pal programming PD3024
Contextual Info: FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 Lattice/Vantis PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 100 mA ICC ■ TTL-level register preload for testability ■ As fast as 7.5 ns maximum propagation delay

Contextual Info: COM’L: H-7/10/15/20 IND: H-7/10/15/20 * Advanced Micro Devices PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 100 mA Ice ■ TTL-level register preload for testability ■ As fast as 7.5 ns maximum propagation delay