TTL BUFFER Search Results

740L6000

Abstract: transistor c2026 c2026 c2026 transistor data 740L6010 transistor equivalent c2026 740L6011 C2026 TRANSISTOR 740L6001 c2037
Contextual Info: HIGH-SPEED LOGIC-TO’LOGIC OPTOCOUPLERS OPTOELECTRONICS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTLto ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT TTL 740L6000 LSTTL TTL 740L6001 LSTTL CMOS 740L6010 LSTTL CMOS 740L6011 LSTTL

MSI Logic

Abstract: UT54ACS14E ut54acts541e UT54ACTS02E UT54ACS14 Tri-State Buffer CMOS cmos msi data book cmos TTL LOGIC DATA BOOK UT54ACS373
Contextual Info: Aeroflex MSI Logic IBIS model Buffer Identification 4/16/2009 Tri-State Devices Input Buffer CMOS TTL Output Buffer 8mA 8mA UT54ACS273 UT54ACTS04 CMOS CMOS E TTL TTL (E) 8mA 8mA 8mA 8mA UT54ACS273 UT54ACS02E UT54ACTS04 UT54ACTS08E CMOS TTL 8mA 8mA UT54ACS273

PDU-1316F-1

Abstract: PDU-1316F-10 PDU-1316F-12 PDU-1316F-2 PDU-1316F-3 PDU-1316F-4 PDU-1316F-5 PDU-1316F-6 PDU-1316F-8 1316F
Contextual Info: Digitally Programmable Delav1 Units series : PDU-1316F 4-Bit TTL Interfaced Specifications: Features: • Input & output TTL buffered ■ 4-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced

PDU-1364F-1

Abstract: PDU-1364F-10 PDU-1364F-2 PDU-1364F-3 PDU-1364F-4 PDU-1364F-5 PDU-1364F-6 PDU-1364F-8 32-RK
Contextual Info: - Digitally Programmable Delay Units PDU-1364F :L'g SERIES: 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced

2n2222 fairchild

Abstract: 74OL60XX
Contextual Info: 74OL6000, 74OL6001, 74OL6010, 74OL6011 Optoplanar High-Speed Logic-to-Logic Optocouplers LSTTL to TTL Buffer TTL Inverter CMOS Buffer CMOS Inverter Description 74OL6000 74OL6001 74OL6010 74OL6011 Features • Industry first LSTTL to TTL and LSTTL to CMOS

Contextual Info: data delayW devicesYinc Digitally Programmable Delay Units SERIES: PDU-13256 8 Bit TTL Interfaced Specifications: • ■ ■ ■ ■ Features: ■ Input & output TTL buffered ■ 8-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting

ttlpd

Abstract: 125OC TTLPD-10 TTLPD-10M TTLPD-15 TTLPD-15M TTLPD-20 TTLPD-25 TTLPD-30
Contextual Info: TTLPD Series FAST / TTL Pulse Width Discriminator Modules Electrical Specifications at 25OC FAST / TTL Pulse Width Discriminator Modules 14-Pin Package Commercial and Mil-Grade Versions FAST/TTL Logic Buffered Pass Pulse Widths above & suppress Pulses below Nominal Value

Contextual Info: Digitally Programmable Delay Units SERIES: PDU-1364F 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely Interfaced ■ Compact & low profile

Contextual Info: Digitally Programmable Delay Units SERIES: PDU-1364F 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced ■ Compact & low profile

Contextual Info: Digitally Programmable data \<?^V delayW Delav* Units series : PDU-1316F devicesYkic. 4-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 4-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced

transistor c2026

Abstract: c2026 transistor data 740L6000 c2028 transistor data C2036 c2026 transistor equivalent c2026 C2037 transistor C2003 740L6000 equivalent
Contextual Info: eu HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS OPTOELECTRONICS OPTO/LOGIC TTL BUFFER TTLINVERTER CMOS BUFFER CMOS INVERTER LSTTL to \ TM ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT 740L6000 LSTTL TTL TTL 740L6001 LSTTL 740L6010 LSTTL CMOS 740L6011 LSTTL

Contextual Info: Digitally Programmable data delay Delay Units SERIES: PDU-1364F d evices^ 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely Interfaced

AI3D-12

Abstract: AI3D-15 AI3D-20 AI3D-25 AI3D-30 AI3D-35 AI3D-10 AI3D-11
Contextual Info: AI3D Series FAST / TTL Buffered Triple Independent Delays Electrical Specifications at 25OC 14-Pin Package Surface Mount and Thru-hole Versions Delay Tolerance ns FAST/TTL Logic Buffered 14-Pin 74F/TTL Buffered Triple Independent Delays DIP P/N G-SMD P/N

ttlpwg

Abstract: 125OC TTLPWG-10 TTLPWG-15 TTLPWG-20 TTLPWG-25 TTLPWG-30 TTLPWG-35 "FAST TTL"
Contextual Info: TTLPWG Series FAST / TTL Pulse Width Generator Modules Electrical Specifications at 25OC 14-Pin Package Commercial and Mil-Grade Versions FAST / TTL Buffered Pulse Width Generator Modules FAST/TTL Logic Buffered Part Number Precise Pulse Width Output triggered by Rising Edge of Input

DTZM1

Abstract: DTZM13 125OC DTZM1-13 DTZM1-17 DTZM1-20 DTZM1-25 DTZM1-30 DTZM1-35 DTZM1-40
Contextual Info: DTZM Series FAST / TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25OC 14-Pin Package Commercial and Mil-Grade Versions TTL Buffered 5 Tap Modules FAST/TTL Logic Buffered 5 Equal Delay Taps Operating Temperature Ranges 0OC to +70OC, or -55OC to +125OC

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

PDU-13256 Series Programmable Delay Units

Abstract: T255 TI28
Contextual Info: data /£ \ Digitally Programmable delay Delay Units SERIES: PDU-13256 devicesVinc. (8 Bit TTL Interfaced S p e cific atio n s : • ■ ■ ■ ■ Features: ■ Input & output TTL buffered ■ 8-BIT TTL program mable delay line ■ Two (2) separate outputs; inverting

Contextual Info: DTZM Series FASTI TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25°C 14-Pin Package Commercial and Mil-Grade Versions TTL Buffered 5 Tap Modules FAST/TTL Logic Buffered 5 Equal Delay Taps Operating Temperature Ranges CPC to +7CPC, or -55°C to +125°C

JESD22-A114-A

Abstract: JESD78
Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL-Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high-speed non-inverting buffer in ultra-small footprint. The device input is compatible with TTL-type input thresholds and the output has a full 5.0 V CMOS level output swing.

Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing.

Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing.

Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing.

ic 8pin ttl

Contextual Info: AMDM Series FAST / TTL Buffered 5-Tap Delay Modules • Low Profile 8-Pin Package Electrical Specifications at 25°C Two Surface Mount Versions FAST/TTL 5-tap 8-Pin DIP • FAST/TTL Logic Buffered Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <13ns Tap 1 Tap 2

IC TTL 74LS00

Abstract: TTL LS 7400 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 TTL 7400 rise and fall time of ic 74ls00 74LS00 gate
Contextual Info: Design Considerations, Testing and Applications Assistance Form FAST AND LS TTL FAST AND LS TTL DATA 3-1 3 DESIGN CONSIDERATIONS SELECTING TTL LOGIC. TTL Families may be mixed in a system for optimum performance. For instance, in new designs, ALS would commonly be used in non-critical speed paths to minimize power consumption while FAST TTL would be used in high