TTL 111 Search Results

BASIC step 1

Contextual Info: Precision Digital Step Attenuator 50Ω TTL Control, Pin Diode Maximum Ratings Operating Temperature -55°C to 100°C Storage Temperature -55°C to 125°C Input Power 15 dBm DC Voltage 5.5 V TTL 5.5V Pin Connections RF IN 4 RF OUT 11 TTL CONTROL #1 2 TTL CONTROL #2

4816

Contextual Info: Precision Digital Step Attenuator 50Ω TTL Control, Pin Diode Maximum Ratings Operating Temperature -55°C to 100°C Storage Temperature -55°C to 125°C Input Power 15 dBm DC Voltage 5.5 V TTL 5.5V Pin Connections RF IN 4 RF OUT 11 TTL CONTROL #1 2 TTL CONTROL #2

DTL or TTL integrated logic circuits

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450APC

Abstract: 9109 DC fairchild ECL 75450a
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75452ATC

Abstract: 75452A
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

754538

Abstract: 9109 DC 55450B 75450BDC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

mw 137

Abstract: fairchild ECL
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

Contextual Info: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

Contextual Info: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

DP8481

Contextual Info: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

MM5280

Abstract: ds75361 DS75361N C1995 MM5270 ds7536
Contextual Info: DS75361 Dual TTL-to-MOS Driver General Description Features The DS75361 is a monolithic integrated dual TTL-to-MOS driver interface circuit The device accepts standard TTL input signals and provides high-current and high-voltage output levels for driving MOS circuits It is used to drive

intel 3207

Abstract: DS75365N C1995 DS75365 DS75365WM M16B N16A vc2f A24V-4
Contextual Info: DS75365 Quad TTL-to-MOS Driver Y General Description Y The DS75365 is a quad monolithic integrated TTL-to-MOS driver and interface circuit that accepts standard TTL input signals and provides high-current and high-voltage output levels suitable for driving MOS circuits It is used to drive

Contextual Info: Precision TOAT-3610+ TOAT-3610 Digital Step Attenuator 50Ω TTL Control, Pin Diode Maximum Ratings Operating Temperature -55°C to 100°C Storage Temperature -55°C to 125°C Input Power 15 dBm DC Voltage 5.5 V TTL 5.5V Pin Connections RF IN 4 RF OUT 11 TTL CONTROL #1

Contextual Info: TOAT-124+ TOAT-124 Precision Digital Step Attenuator 50Ω TTL Control, Pin Diode Maximum Ratings Operating Temperature -55°C to 100°C Storage Temperature -55°C to 125°C Input Power 15 dBm DC Voltage 5.5 V TTL 5.5V Pin Connections RF IN 4 RF OUT 11 TTL CONTROL #1

Contextual Info: PLDM7 Series TTL Logic 3-Bit Programmable Delay Modules Electrical Specifications at Initial Error ref. Referenced to “000“ - Delay ns per Program Setting (P3*P2*P1) 3-Bit TTL

lcd Voltmeter

Abstract: CXA3197 HI3197 HI3197JCQ C2274
Contextual Info: HI3197 Data Sheet October 1998 10-Bit, 125 MSPS D/A Converter • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits • Conversion Rate HI3197JCQ -20 to 75 125 MSPS PECL 100 MSPS (TTL) • Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL

7SEG COM ANODE

Abstract: 7-seg 7-seg ANODE COMMON 7seg D143 TTL 74LS48 TTL 7446 decoder 74LS48 7448 decoder decoder 74LS47
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Cont'd 5.5 H — 125 D141 4L.6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I.6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes No Yes

Contextual Info: December 1989 Semiconductor DM74ALS37A Quadruple 2-Input NAND Buffer Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with LS TTL counterpart Improved AC performance over LS37 Improved line receiving characteristics

PLCC44 pinout

Abstract: plcc44 pinout numbers 8 shift register by using D flip-flop 74F154 shift register by using D flip-flop 3 bit magnitude comparator octal inverter schmitt trigger non inverting 74f3037 SOT27-1
Contextual Info: Philips Semiconductors Functional Index IC15: FAST TTL LOGIC SERIES Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10V21

Abstract: F TTL family characteristics MM74C904N C1995 MM54C901 MM54C902 MM54C903 MM54C904 MM74C901 MM74C902
Contextual Info: MM54C901 MM54C902 MM54C903 MM54C904 MM74C901 Hex Inverting TTL Buffer MM74C902 Hex Non-Inverting TTL Buffer MM74C903 Hex Inverting CMOS Buffer MM74C904 Hex Non-Inverting CMOS Buffer General Description Features These hex buffers employ complementary MOS to achieve

Contextual Info: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.

VSC7125

Abstract: AN-20 T9631
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet 1.0625 Gbits/sec Fibre Channel Transceiver VSC7125 Features • ANSI X3T11 Fibre Channel Compatible 1.0625 Gbps Full-duplex Transceiver • 106.25 MHz TTL Reference Clock • 10 Bit TTL Interface for Transmit and