TRUTH TABLE FOR 7 INPUTS OR GATE Search Results

GDFP1-G14

Abstract: CDFP2-F14 GDFP1-F14
Contextual Info: INCH-POUND MIL-M-38510/757C 14 November 2003 SUPERSEDING MIL-M-38510/757B 14 March 2003 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, ADVANCED CMOS, BUFFER GATES, MONOLITHIC SILICON, POSITIVE LOGIC Reactivated after 14 Nov. 2003 and may be used for new and existing designs and acquisitions.

20-HSOP

Contextual Info: Freescale Semiconductor Technical Data Document Number: MC33186 Rev. 8.0, 4/2013 H-Bridge Driver 33186 The 33186 is a monolithic H-Bridge ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low

HA11-7

Contextual Info: european space agency agence spatiale européenne Pages 1 to 51 INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS SILICON GATE, STATIC 256K 32768x8 BIT ASYNCHRONOUS RANDOM ACCESS MEMORY WITH 3-STATE OUTPUTS, BASED ON TYPE M65656 ESA/SCC Detail Specification No. 9301/030

Contextual Info: SPECIFICATION MHS/SCC034 Rev B June, 2000 Page 1 of 62 PROJET SPACE GENERAL TITLE INTEGRATED CIRCUIT, SILICON MONOLITHIC, CMOS SILICON GATE 8192 X 16 DUAL PORT RANDOM ACCESS MEMORY WHICH ALLOWS SIMULTANEOUS READS OF THE SAME MEMORY LOCATION WITH 3-STATE OUTPUTS BASED ON TYPES M67025E.

LS155

Abstract: demultiplexer truth table LS156 T74LS156 74 ls 155 demultiplexer
Contextual Info: in i ss DUAL 1-0F-4 DECODER/DEMULTIPLEXER DESCRIPTION The TTL/MSI T54LS155/T74LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­ multiplexers. These devices have two decoders with common 2-bit Address inputs and separate ga­ ted Enable inputs. Decoder “ a” has an Enable gate

T74LS136B1

Contextual Info: SGS 0^ QUAD 2-INPUT EXCLUSIVE OR GATE DESCRIPTION The T54LS136/T74LS136 is a high speed QUAD 2-INPUT EXCLUSIVE OR GATE with open collec­ tor output fabricated in LOW POW ER SCHOTTKY technology. 1 B1 Plastic Package D1/D2 Ceramic Package M1 Micro Package

74LS155

Abstract: truth table for 4 to 16 decoder 74ls156 LS155 truth table for 1 to 16 decoder 74LS155 DATASHEET DOWNLOAD LS156 SN54LSXXXJ 2 to 4 decoder for ttl circuit 4 to 16 decoder for ttl circuit
Contextual Info: SN54/74LS155 SN54/74LS156 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an

MIL-STD-806

Abstract: 4-1 MULTIPLEXER IC
Contextual Info: 4-1 H o w to Read M IL Type Logic Sym bols Table 4-1 shows the MIL type logic symbols used in high-speed CMOS IC. This logical chart is based on MIL-STD-806. Clocked inverter and transmission gate employ specific symbols. Table 4-1 Circuit Function MIL Logic Symbols

SN74LS47N PIN DIAGRAM

Abstract: SN74LS47N SN74LS47N DATASHEET of SN74LS47N SN74LS47 SN74LS47N pin configuration SN74LS47D SN74LS47N WITH 7 SEGMENT DISPLAY
Contextual Info: SN74LS47 BCD to 7-Segment Decoder/Driver The SN74LS47 are Low Power Schottky BCD to 7-Segment Decoder/ Drivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving indicators directly. Seven NAND gates and one

MIL-STD-806

Abstract: 4-1 MULTIPLEXER IC
Contextual Info: 4-1 How to Read MIL Type Logic Symbols Table 4-1 shows the MIL type logic symbols used in high-speed CMOS IC. This logical chart Is based on MIL-STD-806. Clocked inverter and transmission gate employ specific symbols. Table 4-1 Circuit Function M IL Logic Symbols

T74LS164B1

Abstract: T74LS164 LS164 T54LS164D2 8 indipendent diode circuit aag2
Contextual Info: SERIAL-IN PARALLEL-OUT SHIFT REGISTER DESCRIPTION The T54LS164/T74LS164 is a 8-Bit Serial-ln Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which

T54LS166

Abstract: T54LS166D2 T74LS166 T74LS166B1
Contextual Info: as. 8-BIT SHIFT REGISTER DESCRIPTION The T54LS/T74LS166 is an 8-bit shift register. It consists of a parallel-in or serial-in, seriai-out 8 bit shift register with gated clock inputs and an over­ riding clear input. The parallel-in or serial-in mo­ des are controlled by the SHIFT/LOAD input. When

74LS164 PIN DIAGRAM

Abstract: 74LS164 LS164 4 inputs OR gate datasheet 4 inputs OR gate truth table 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS164 SERIAL-IN PARALLEL-OUT SHIFT REGISTER The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous

T74LS86B1

Abstract: T74LS86 T54LS86D2 S-7975
Contextual Info: s e s QUAD 2-INPUT EXCLUSIVE OR GATE D E S C R IP T IO N The T54LS86/T74LS86 is a high speed QUAD 2-INPUT EXCLUSIVE OR GATE fabricated in LOW POWER SCHOTTKY technology. 1 B1 Plastic Package D1/D2 Ceramic Package «W * M1 Micro Package C1 Plastic Chip Carrier

TTL 74ls86

Abstract: 4 inputs OR gate truth table 74ls86 74LS86 truth table 74ls86 datasheet SN54/74LS86 schottky 74LS86 5 inputs OR gate truth table 74LS86 ttl truth table NOT gate 74
Contextual Info: SN54/74LS86 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 1 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 TRUTH TABLE IN OUT A B Z L L H H L H L H L H H L 14 1

HCF4095B

Abstract: HCF4095BEY HCF4095BM1 HCF4095M013TR
Contextual Info: HCF4095B GATED J-K MASTER SLAVE FLIP-FLOP • ■ ■ ■ ■ ■ ■ 16MHz TOGGLE RATE Typ. at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C

Contextual Info: ss QUAD 2-INPUT EXCLUSIVE OR GATE DESCRIPTION The T54LS86/T74LS86 is a high speed QUAD 2-INPUT EXCLUSIVE OR GATE fabricated in LOW POWER SCH OTTKY technology. 1 B1 Plastic Package D1/D2 Ceramic Package S S M1 Micro Package C1 Plastic Chip Carrier ORDERING NUMBERS:

Contextual Info: PRELIMINARY CY7C1344A/GVT7164B36 64K x 36 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • The CY7C1344A/GVT7164B36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

HCF4095BE

Abstract: HCF4095B HCF4095BEY HCF4095BM1 HCF4095M013TR
Contextual Info: HCF4095B GATED J-K MASTER SLAVE FLIP-FLOP • ■ ■ ■ ■ ■ ■ 16MHz TOGGLE RATE Typ. at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C

Contextual Info: s s SERIAL-IN PARALLEL-OUT SHIFT REGISTER DESCRIPTION The T54LS164/T74LS164 is a 8-Bit Serial-ln Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which

Contextual Info: TO SHIBA TC55V1325FF-7,-8,-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V1325FF is a 1,048,576-bit synchronous pipelined burst static random access memory SRAM

Contextual Info: TO SHIBA TC55V1325FF-7,-8,-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V1325FF is a 1,048,576-bit synchronous pipelined burst static random access memory SRAM

Contextual Info: 344A PRELIMINARY CY7C1344A/GVT7164B36 64K x 36 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • The CY7C1344A/GVT7164B36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

Contextual Info: TOSHIBA TC55V1325FF-7,-8,-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V1325FF is a 1,048,576-bit synchronous pipelined burst static random access memory SRAM