TRANSM Search Results

tmp8251

Abstract: 74ls04n 74LS04 Fan Out
Contextual Info: TOSHIBA LASER/FBR OPTIC TGD D D W72S2 G O l b O M ? 3 T1 E T O S b TOSLINK TOHL50, consisting of a highly reliable optical transmitting module TOTX5C) a n d a r e c e i v i n g m o d u l e T O R X 5 0 , i s a n i n d u s t r i a l - u s e d i g i t a l f i b e r o p t i c

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

74LS299 APPLICATIONS

Abstract: 74ls74 timing setup hold pin diagram and block diagram of 74ls74 ANSI32
Contextual Info: TMS320SA32 32 KBIT/S ADPCM TRANSCODER NOVEMBER 1986 N PACKAGE ANSI 32 kbit/s ADPCM Compatible TOP VIEW CCITT G.721 32 kbit/s ADPCM Compatible Half-Duplex Transcoder Operation Transmit/Receive Selection Option /t-Law/A-Law PCM Selection Option NC£ 1^ 4 0 □

TODX2102

Contextual Info: TOSHIBA TOSLINK TODX2102 Unit mm Preliminary Fiber Optic Transceiving Module for 10 MAX. 39.3 MAX. 3.3 Duplex SC Connector F-type Features • Data rate: 10 to 155 M b/s (NRZ code) • Transmission distance: up to 2000m • Single +5V voltage • Shifted ECL interface

74F138

Contextual Info: S N 5 4 F13 8 , S N 74 F13 8 3-LINE TO 8-LINE D EC O D ERS/D EM U LTIPLEXERS D2932, MARCH 1987 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 54F138 . . . J PACKAGE SN 74F138 . . . D OR N PACKAGE TOP VIEW AC 1 U ,6 3 vcc

Contextual Info: TOSHIBA TC74AC164 8-bit Shift Register S-IN, P-OUT Features: • High Speed: fmax = 170MHz (typ.) at Vco = 5V • Low Power Dissipation: • High Noise Immunity: VN,H=VNIL=28% Voc (min.) • Symmetrical Output Impedance: llOHl = I o l = 24mA (min.). Capability of driving 50ft transmission lines.

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

D3318

Contextual Info: 74AC11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER D3318, JULY 1989 - R EV ISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems * Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception

TCM2912

Abstract: TCM2912C
Contextual Info: TCM2912C PCM LINE FILTER D2788, SEPTEMBER 1983-REVISED DECEMBER 1987 High-Pass Transmit Filter for Rejection of All Low-Frequency Noise: 16 Hz . 7 0 dB Typical 5 0 Hz . 3 5 dB Typical

LS138

Abstract: SN54ALS138
Contextual Info: TYPES SN54ALS138, SN54AS138, SN74ALS138, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D 2 6 6 1 , APRIL 1 9 8 2 — REVISED DECEMBER 1 9 8 3 Designed Specifically for High-Speed Mem ory Decoders and Data Transmission Systems SN 54A LS138, SN 54A S 138 .

TA 55122

Contextual Info: SN55122, SN75122 TRIPLE LINE-RECEIVERS D 1 3 3 4 , SEPTEMBER 1 9 7 3 Designed for Digital Data Transmission Over Coaxial Cable, Strip Line, or Twisted Pair REVISED SEPTEMBER 1 9 8 6 S N S 5 1 2 2 . . . J PACKAGE S N 7 5 1 2 2 . . . D , J. OR N PACKAGE ITO P V IE W

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

Contextual Info: SN75ALS193 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS D2931. JUNE 1 9 8 6 - REVISED AUGUST 1989 Meets EIA Standards RS-422-A and RS-423-A J PACKAGE ITOP VIEW Meets CCITT Recommendations V.10, V.11, X.26, and X.27 Designed for Multipoint Bus Transmission on

Contextual Info: BATA TRANSMISSION R e d u c e Y o u r C a b le C o s t s w it h L V D S S e r ia liz e r / D e - s e r ia liz e r SNG5LVD S9 3 , SNE5LVDS94 > • S U S in ► SNB5 LVD S9 5 , SN65LVDS96 > S8.35 i» quantitits of 18BB ► E V IV I T he new est Low Voltage bus structures with no loss in data

042b

Contextual Info: 74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B - MAY 1988 - REVISED A P R IL I 996 D, N, OR PW PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Y1 [ 1 Y2 [ 2 Incorporates Three Enable Inputs to

8 channel remote control transmitter circuit

Abstract: 8 channel rf remote control remote control Pulse Position Modulation circuit SN75605
Contextual Info: PRE!.I!1IÎ!AnY APRIL 1980 ADVANCED CIRCUITS SN76605N REMOTE CONTROL TRANSMITTER CHlAb 002926 • Low Icc due to I*L technology. ] 16 MODULATION SWITCH TIMING CURRENT CONTROL 2[ ] 15 EXTERNAL MODULATION CHI ON/OFF CONTROL 3[ 3w RF VCC CH2 ON/OFF CONTROL •»[

Contextual Info: 74ACT11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER SCASI 75A - SEPTEMBER 1991 - REVISED APRIL 1996 • Inputs Are TTL-Voltage Compatible • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D, N, OR PW PACKAGE TOP VIEW

2SC2075

Abstract: 2SC207S 27mhz rc circuit 2SC2075A
Contextual Info: SILICON NPN EPITAXIAL T Y P E 2SC2075 27MHz POWER AMPLIFIER APPLICATIONS. Unit in mm 03.6±O .2 FEATURES : 31n '0 • Recommended for Output Stage Application of AM 4W Transmitter. & • High Power Gain. • Wide Area of Safe Operation. MAXIMUM RATINGS Ta=25°C

Contextual Info: 74ACT11139 DUAL M IN E TO 4-LINE DECODER/DEMULTIPLEXER SCASI 75 - D3907, SEPTEMBER 1991 - REVISED APRIL 1993 D, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems

SN7516

Abstract: SN75162 SN75LBC786
Contextual Info: DATA TRANSMISSION RS - 4 23 S t a nd a r d S e l e c t i o n Gui de Footprint Device Name M ax M ax Drvr/Rcvr Supply tpd Current ns (mA) Driver Pricing for Sle w Rate !K units Control ($> Package Options Temperature Range M u lt ip le S u p p ly , 5 V an d + 1 2 V

Contextual Info: TL16C550B ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS136A - JANUARY 1994 - REVISED MARCH 1996 • Capable of Running With All Existing TL16C450 Software • After Reset, All Registers Are Identical to the TL16C450 Register Set • In the FIFO Mode, Transmitter and Receiver

Contextual Info: SN54HC139, SN74HC139 DUAL 2 LINE TO 4-LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 D esigned S pecifically for H igh-Speed S N 5 4 H C 1 3 9 . . . J PACKAGE S N 7 4 H C 1 3 9 . . . O W OR N PACKAGE M e m o ry D ecoders and D ata Transm ission

37C15

Contextual Info: TCM37C13, TCM37C14, TCM37C15 PCM COMBO WITH PROGRAMMABLE GAIN CONTROL S L W S 0 1 8 - JUNE 1996 • Meets CCITT/ D3/D4 Channel Bank Recommendations for Input Signals Greater than -5 5 dBmO • Programmable Transmit and Receive Gain Control with Pin-Selectable

LVDS050

Abstract: LVDS051 LVDS180 SN65LV0S050
Contextual Info: DATA TRANSMISSION Increase Signaling Rates and Low er Pow er w ith LVDS Dual and Single Drivers/Receivers SN65LV0S050, SN65LVDS051 > $ 3 .74 in q u an tities o f 1000 SN65LVDS17S > - S 2 .1 3 in q u an titie s o f l i O L ow Voltage Differential Signaling