TP 8370 Search Results

MT4C16257DJ-6

Contextual Info: 256K X 16 FPM DRAM MICRON I TECHNOLOGY, INC. DRAM MT4C16257 FEATURES • In d u stry -sta n d a rd x l6 p in o u ts, tim ing, functions an d packages • H igh-perform ance CM OS silicon-gate process • Single +5V +10% p o w er su p p ly • All in p u ts, o u tp u ts an d clocks are TTL-com patible

SH 6770

Abstract: IC 7870 Y136 tes 1310 CL21 105 j KS0788 tp 8370 om 8370 Y143 88 80CH
Contextual Info: PRELIMINARY CMOS DIGITAL INTEGRATED CIRCUIT KS0788 Introduction KS0788 is a se gm e n t and c o m m o n d rive r w ith 160 channel fo r a large scale d o t m a trix LCD. This device is LCD d rive r having m ulti o u tp u t, 1/400 duty. LCD d rivin g vo lta g e o f th is d e vice is 40 V .

MT4C1024E

Abstract: MT4C1024E-12 MT4C4256E
Contextual Info: M IC R O M ERRATA DATA SHEET • TKHNOUXW. MC. 2805 East Columbia Road Bolso, Idaho 83706 TEL. 208 386-3900 TWX 910-970-5973 Q uality • Perform ance • Service r - v é -2.3- i f (1 MEG PAGE MODE DRAM) MT4C1024E MT4C4256E FEATURES • • • • •

Contextual Info: ID E MICRON TECHNOLOGY INC D J b lllS iH OOOOSbE 0 ERRATA DATA SHEET I |U | TCCHNOUXW. WC. d 2805 East Columbia Road Bolse, Idaho 83706 i TEL. 208 386-3900 TW X 910-970-5973 Q u a lity • P erform ance • S ervice T-Vé-2,3 ->5 (1 MEG PAGE MODE DRAM) MT4C1024E

Contextual Info: MICRON8 I 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM TEOWOLOOV, INC. 2Mb SYNCBURST SRAM MT58LC128K18D9, MT58LC64K32D9, MT58LC64K36D9; MT58LC128K18G1, MT58LC64K32G1, MT58LC64K36G1 3.3V V dd, 3.3V or 2.5V I/O, Pipelined, Single-Cycle Deselect

Contextual Info: 2 M b : 1 2 8 K X 1 8 , 6 4 K x 3 2 /3 6 P IP E L IN E D , D C D S Y N C B U R S T S R A M M I^ E a n N * I MT58LC128K18C6, MT58LC64K32C6, MT58LC64K36C6; MT58LC128K18F1, MT58LC64K32F1, MT58LC64K36F1 2Mb SYNCBURST SRAM 3.3V V dd, 3.3V or 2.5V I/O, Pipelined, Double-Cycle

Contextual Info: lU II^ E 3 H N I 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM O I M I I > C V M P D I ID O T Z IV ID O Y I M U D U n O I O D A A il O n IV I MT58LC128K18B4, MT58LC64K32B4, MT58LC64K36B4; MT58LC128K18E1, MT58LC64K32E1, MT58LC64K36E1 3 .3 V V dd , 3.3V or 2.5V I/O, Flow-Through

Contextual Info: ADVANCE MICRON8 I 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM TEOWOLOOV, INC. MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 8Mb SYNCBURST SRAM 3.3V Supply, 3.3V or 2.5V I/O, Flow-Through FEATURES Fast access tim es: 6.8ns, 7.5ns, 8.5ns, 9ns a n d 10ns

9114s

Contextual Info: ADVANCE MICRON I 256K X TECHNOLOGY, WC. 256Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST COUNTER FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View Fast access times: 4.5, 5, 5.5 an d 6ns

Contextual Info: ADVANCE MICRON8 I 8Mb: 512K x 18, 256K x 32/36 PIPELINED, SCD SYNCBURST SRAM TEOWOLOOV, INC. MT58L512L18P, MT58L256L32P, MT58L256L36P; MT58L512V18P, MT58L256V32P, MT58L256V36P 8Mb SYNCBURST SRAM 3.3V Supply, 3.3V or 2.5V I/O, Pipelined, Single-Cycle Deselect

6502 microprocessor

Abstract: plessey cla 3000 crompton K-50-50 ferranti ztx SP92701 draw pin configuration of ic 7404 SP9754
Contextual Info: DATA CONVERTERS & Voltage References IC Handbook APLE SSE Y Sem iconductors Foreword The collective description of Data Conversion covers a vast range of applications which is limited only by the imagination of today’s system designers. Traditionally the name of Plessey

Marking E5

Contextual Info: 1 MEG x 16 EDO DRAM DRAM MT4LC1M16E5 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • JEDEC- an d in d u stry -sta n d a rd x l6 tim ing, functions,

Contextual Info: 1 MEG x 16 EDO DRAM M IC R O N I TECHNOLOGY, INC. DRAM MT4LC1M16E5 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • JEDEC- an d in d u stry -sta n d a rd x l6 tim ing, functions,

Contextual Info: ADVANCE MICRON I 128K TECHNOLOGY, WC. 128Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST COUNTER FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View 100-Pin TQFP

Contextual Info: ADVANCE M I IC n D N 25 6 K x 1 8 / 1 2 8K x 36 LVTTL, F L O W - T H R O U G H LATE WRITE SRAM MT59L256L18F MT59L128L36F 4.5Mb LATE WRITE SRAM Dual Clock and Single Clock FEATURES * * * * * * * * * * * * * * * * * Fast cycle tim es 5ns, 6ns and 7ns 256K x 18 or 128K x 36 configurations

MT4C4007JDJ

Contextual Info: ADVANCE M T 9 D 1 3 6 A X, M T 1 8 D 2 3 6 A X 1 MEG, 2 MEG x 36 DR AM M O D U L E S DRAM MODULE 1 MEG, 2 MEG x 36 4, 8 MEGABYTE, 5V, ECC, EDO PAGE MODE FEATURES * * * * * * * * PIN ASSIGNMENT Front View Four CAS# ECC p in o u t in a 72-pin, single-in-line

Contextual Info: M I^ E a n N * I 1 Mb: 64K X 18, 32K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM MT58LC64K18C6, MT58LC32K32C6, MT58LC32K36C6 1Mb SYNCBURST SRAM 3 .3V Vdd, 3.3V I/O, Pipelined, Double-Cycle Deselect FEATURES Fast access tim es: 3.5ns, 3.8ns, 4.2ns, 4.5ns a n d 6ns

Contextual Info: MT4C1 6270 256K X 16 DRAM MICRON I TECHNOLOGY, INC. DRAM 256K 1 6 DRAM X 5V, EDO PAGE MODE FEATURES In d u stry -stan d ard x l6 p in ou ts, tim in g , fu nction s and p ackages * H ig h -p erfo rm an ce C M O S silico n -g ate process * Single + 5 V ±10% p o w er supp ly*

Contextual Info: M I^ E a n N * I 1 Mb: 64K X 18, 32K x 32/36 3.3V I/O, PIPELINED, SCD SYNCBURST SRAM MT58LC64K18D9, MT58LC32K32D9, MT58LC32K36D9 1Mb SYNCBURST SRAM 3 .3V Vdd, 3.3V I/O, Pipelined, Single-Cycle Deselect FEATURES Fast access tim es: 3.5ns, 3.8ns, 4.2ns, 4.5ns a n d 6ns

MT58LC32K32B4

Abstract: marking abw
Contextual Info: M I^ E a n N * I 1 Mb: 64K X 18, 32K x 32/36 3.3V I/O, FLOW-THROUGH SYNCBURST SRAM 1M b SYNCBURST SRAM S c ™ ' MT58L032K32B4' 3.3V Vdd, 3.3V I/O, Flow-Through FEATURES • • • • • • • • • • • • • • • Fast access tim es: 6.8ns, 7.5ns, 8.5ns, 9ns a n d 10ns

Contextual Info: M i r a r i M I . V J L Z m t 4 C 4 M 4 a i S 4 MEG X 4 DRAM DRAM 4 MEG x 4 DRAM 4K REFRESH, 5.0V, FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES PIN A S S I G N M E N T (Top View) * JED EC- and in d u stry -stan d ard x4 p in o u t, tim ing,

58LC

Contextual Info: ADVANCE MICRON I 64K TECHNOLOGY, N C . 64Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST COUNTER FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View 100-Pin TQFP

Contextual Info: ADVANCE MT36LD872A X 8 MEG X 72 DRAM MODULE DRAM IU I Q Q I I IV IV J V J \ J 8 MEG x 72 I P L . 1— 6 4 M E G A B Y T E , E C C , N O N B U F F E R E D , 3 .3 V , 8 C A S#i FA ST PA G E o r ED O PA G E M ODE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM

Contextual Info: F Fno«M Pll/I D m ic r o n I TECHNOLOGY, INC. DRAM MT4LC4M16F5 For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES PIN ASSIGNMENT Top View • Single +3.3V +0.3V p o w er su p p ly