TOGGLE FLIP FLOP IC Search Results

14027B

Abstract: HD14027B
Contextual Info: HD14027B Dual J - K Flip Flop The HD14027B dual J-K flip-flop has independent J, K, Clock C , Set(S) and Reset(R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. • PIN ARRANGEMENT ■ FEATURES • • •

Single Toggle Flip Flop

Abstract: AT40K AT40KAL AT94K AT94KAL Single T-Type Flip-Flop
Contextual Info: IP Core Generator: Flip-Flop Features • Flip-Flop – D-Type • Flip-Flop – Toggle • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices

Contextual Info: SY10E131 SYNERG Y 4-BIT D FLIP-FLOP OTlUltlJl SEMICONDUCTOR DESCRIPTION FEATURES • 1100 MHz min. toggle frequency. The SY10E/100E/101E131 is a high speed quad master-slave D-type flip- flop with differential outputs designed for use in new high performance ECL systems. The flip-flops may be individually

cd40138

Abstract: CD4013B RCA-CD4013B CD4013BH d flipflop 15-V
Contextual Info: CD4013B Types Features: CMOS Dual ‘D’-Type Flip-Flop • Set-Reset capability ■ Static flip-flop operation — retains state indefinitely with clock level either "high" or "low ” ■ Medium-speed operation — 16 MHz typ. clock toggle rate at 10V

14013B

Contextual Info: H D 14013B Dual D -ty p e Flip Flop The HD14013B dual type D flip-flop has independent Data, D , Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip-flops for counter and toggle

Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J−K flip−flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip−flop. These devices may be used in control, register, or toggle functions. Features • • • • • • • •

Contextual Info: * HEX D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 700MHz The SY100S351 offers six D-type, edge-triggered, m aster/slave flip-flops with differential outputs, and is designed for use in high-perform ance ECL system s. The

CD4027* free

Abstract: 14027B MC14027BCP MC14027BD MC14027BDR2 MC14027BF MC14027BFEL CD4027B MC14027B
Contextual Info: MC14027B Dual J-K Flip-Flop The MC14027B dual J–K flip–flop has independent J, K, Clock C , Set (S) and Reset (R) inputs for each flip–flop. These devices may be used in control, register, or toggle functions. • • • • • • Diode Protection on All Inputs

Contextual Info: * SY10EL51 SY100EL51 DIFFERENTIAL CLOCK D FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES 475ps propagation delay 2.8GHz toggle frequency Internal 75KH input pull-down resistors ESD protection of 2000V Available in 8-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM

Contextual Info: * FEATURES • ■ ■ ■ SY10E131 SY100E131 4-BIT D FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION 1100MHz mln. toggle frequency Differential output Individual and common clocks individual asynchronous reset ■ Paired asynchronous sets ■ ESD protection of 2000V

Contextual Info: * TRIPLE D FLIP-FLOP SYNERGY SEMICONDUCTOR SY100S331 DESCRIPTION FEATURES • Max. toggle frequency of 800MHz ■ Differential outputs ■ I ee min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

CD4027 application note

Abstract: cd4027 toggle RCA-CD4027A truth table of 4027 CD4027 applications 4027 CMOS Flip-Flop feme CD4027 rca vpg cd4013a
Contextual Info: CD4027A Types CMOS Dual J-K Master-Slave Flip-Flop The C D4027A is useful In perform ing con­ tro l, register, and toggle fun ctio ns. Logic levels present at the J and K inputs along w ith internal self-steering co ntro l th e state o f each flip -flo p ; changes in the flip -flo p

Contextual Info: « SY10EL52 SY100EL52 DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES 365ps propagation delay 2.0GHz toggle frequency Internal 75K£2 input pull-down resistors ESD protection of 2000V Available in 8-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM

Contextual Info: * TRIPLE D FLIP-FLOP SYNERGY SY100S331 SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 800MHz Differential outputs Iee min. o f-80 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for

Contextual Info: *SYNERGY SY10E131 SY100E131 4-BIT D FLIP-FLOP SEMICONDUCTOR FEATURES DESCRIPTION • 1100M Hz min. toggle frequency ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ Differential output ■ Individual and common clocks ■ Individual asynchronous reset

Contextual Info: * SY10E131 SY100E131 4-BIT D FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 1100MHz min. toggle frequency ■ Extended 100E V ee range of -4.2V to -5.5V ■ Differential output ■ Individual and common clocks ■ Individual asynchronous reset ■ Paired asynchronous sets

Contextual Info: * SY10E131 SY100E131 4-BIT D FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 1100MHz min. toggle frequency ■ Extended 100E V ee range of -4.2V to -5.5V ■ Differential output ■ Individual and common clocks ■ Individual asynchronous reset ■ Paired asynchronous sets

AT6005A-4AC

Abstract: Inverter TBE
Contextual Info: Features • High Performance System Speeds > 100 MHz Flip-Flop Toggle Rotes > 250 MHz 1.2 ns/1.5 ns Input Delay 3.0 na/6.0 ns Output Delay • Up to 204 User IIOs • Thousands of Registers • Cache Logic” Design Complete/Partial In-System Reconfiguration

Contextual Info: * 3-BIT DIFFERENTIAL FLIP-FLOP SYNERGY SEMICONDUCTOR FEA T U RES SY10E431 SY100E431 DESCRIPTIO N Differential D, clock and Q V bb output for single-ended use 1100MHz min. toggle frequency Edge-triggered asynchronous set and reset Extended 100E V ee range of -4.2V to -5.46V

Contextual Info: * SYNERGY HEX D FLIP-FLOP SY100S351 SEMICONDUCTOR DESCRIPTION FEATURES Max. toggle frequency of 700MHz Clock to Q max. of 1200ps Iee min. o f-98 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for

d 2331

Abstract: half adder ic number of half adder ic with full specification vts 7070
Contextual Info: VITESSE SEMICONDUCTOR MflE D VITESSE FEATURES • Superior performance: high speed/low power • Array performance: - D flip-flop toggle rates: >1 GHz - Typical gate delay: 177 ps @ 1.1 mW 2-Input NOR, F.O. = 3 ,1 .5 mm wire - TTL/CM O S inputs/outputs to support up to

Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds > 1 0 0 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns Input Delay 3.5 ns Output Delay Thousands of Registers Cache Logic Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State

G52020-0

Abstract: VSC10000
Contextual Info: PRELIMINARY I H T ÏJ Q Ir VSC10000 mm High Performance SEMICONDUCTOR CORPORATION j 0 0 () A fm y Features • High Performance Characteristics VLSI GaAs Gate Array - D flip-flop; Clk to Q: 480 ps, toggle rate > 1GHz; Clk to Q = 588 ps, worst case (F.O. = 3 ,1 .5mm wire)

L084A

Abstract: bl043 bl083 T6005A ed84 L064A
Contextual Info: AT6000/LV Series Features • • • • • • • • • • High Performance System Speeds > 100 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns/1.5 ns Input Delay 3.0 ns/6.0 ns Output Delay Up to 204 User l/Os Thousands of Registers Cache Logic Design