TO133 Search Results

STi5105ALC

Abstract: LQFP216 sti5105 STi5105AYC STV0360 STV6110A STV0297 lqfp-216 stv0299 tuner stv0360
Contextual Info: STi5105 High-performance advanced SD decoder for set-top box Data Brief Features • Enhanced ST20 32-bit VL-RISC CPU – 200 MHz, single cycle cache, 4 Kbyte instruction cache, 4 Kbyte data cache, 2 Kbyte SRAM ■ Unified memory interface – Up to133 MHz,16-bit wide DDR interface

PC133 registered reference design

Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

Contextual Info: User’s Manual V850E/ME2 32-Bit Single-Chip Microcontroller Hardware µPD703111A Document No. U16031EJ3V0UD00 3rd edition Date Published June 2004 N CP(K) Printed in Japan [MEMO] 2 User’s Manual U16031EJ3V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

hitachi sh3

Abstract: 9080RDK-RC32364 MPC860 RC32364 Hitachi DSA0092 pci plx 9080
Contextual Info: PCI 9080RDK-RC32364 Reference Design Kit with PCI SDK Features • PCI Version 2.1 compliant host board based on the powerful PCI 9080 Bus Master I/O Accelerator chip ■ Full Bus Master and Burst Management–Directly supports PCI Target, PCI Initiator and DMA

06505

Abstract: PCK2509S TSSOP24 PC133 registered reference design
Contextual Info: INTEGRATED CIRCUITS PCK2509S 50–150 MHz 1:9 SDRAM clock driver Product specification Philips Semiconductors 1999 Oct 19 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S adjusted to 50 percent, independent of the duty cycle at CLK. Each

LB 11899

Abstract: DS21352 DS21352L DS21352LN DS21552 DS21552L DS21552LN TR54016 TCS 4199
Contextual Info: 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers SCT www.dalsemi.com FEATURES § § § § § § § § § § § § § § § § Complete DS1/ISDN–PRI/J1 transceiver functionality Long and Short haul LIU Crystal–less jitter attenuator Generates DSX–1 and CSU line build outs

CDCF2510

Abstract: CDCF2510PWR CDCVF2510A PC133 registered reference design
Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

CDCF2509

Abstract: CDCF2509PWR CDCVF2509A PC133 registered reference design CDC2509
Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

CDCF2510

Abstract: CDCF2510PWR CDCVF2510A PC133 registered reference design
Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PCK2509SA

Abstract: PCK2509SL PCK2509SLDH PC133 registered reference design
Contextual Info: INTEGRATED CIRCUITS PCK2509SL 50–150 MHz 1:9 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group Philips Semiconductors 2000 Dec 01 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509SL

PCK2510SA

Abstract: PCK2510SL PCK2510SLDH PC133 registered reference design
Contextual Info: INTEGRATED CIRCUITS PCK2510SL 50–150 MHz 1:10 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group Philips Semiconductors 2000 Dec 01 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver

PC133 registered reference design

Contextual Info: CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628C – APRIL 1999 – REVISED MARCH 2001 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

CDCF2509

Abstract: CDCF2509PWR PC133 registered reference design
Contextual Info: CDCF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS624B – APRIL 1999 – REVISED MARCH 2001 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz

PC133 registered reference design

Abstract: CDC2509
Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PC133 registered reference design

Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

Contextual Info: 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers www.maxim-ic.com FEATURES § § § § § § § § § § § § § § § § PIN ASSIGNMENT Complete DS1/ISDN–PRI/J1 transceiver functionality Long and Short haul LIU Crystal–less jitter attenuator Generates DSX–1 and CSU line build-outs

PC133 registered reference design

Abstract: CDC2509
Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PCK2510S

Abstract: PCK2510SPW PC133 registered reference design
Contextual Info: INTEGRATED CIRCUITS PCK2510S 50–150 MHz 1:10 SDRAM clock driver Product specification Supersedes data of 1999 Dec 13 ICL03 — PC Motherboard ICs; Logic Products Group Philips Semiconductors 2001 Feb 02 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

CDCF2510

Abstract: CDCF2510PWR PC133 registered reference design
Contextual Info: CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz

CDCF2509

Abstract: CDCF2509PWR PC133 registered reference design
Contextual Info: CDCF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS624A – APRIL 1999 REVISED MAY 1999 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9