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    Diodes Incorporated DXTN10060DFJBQ-7

    TRANS NPN 60V 4A UDFN2020-3
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    DigiKey () DXTN10060DFJBQ-7 Tape & Reel 10,169 3,000
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    DXTN10060DFJBQ-7 Cut Tape 10,169 1
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    DXTN10060DFJBQ-7 Digi-Reel 10,169 1
    • 1 $0.87
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    Avnet Americas DXTN10060DFJBQ-7 Tape & Reel 48 Weeks 3,000
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    Mouser Electronics DXTN10060DFJBQ-7 119
    • 1 $1.12
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    Newark () DXTN10060DFJBQ-7 Cut Tape 5
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    DXTN10060DFJBQ-7 Tape & Reel 100
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    Avnet Asia DXTN10060DFJBQ-7 42 Weeks 3,000
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    Avnet Silica DXTN10060DFJBQ-7 42 Weeks 3,000
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    Diodes Incorporated DXTN10060DFJBWQ-7

    TRANS NPN 60V 4A W-DFN2020-3
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    DigiKey () DXTN10060DFJBWQ-7 Tape & Reel 5,170 3,000
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    DXTN10060DFJBWQ-7 Digi-Reel 5,170 1
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    DXTN10060DFJBWQ-7 Cut Tape 5,170 1
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    Avnet Americas DXTN10060DFJBWQ-7 Tape & Reel 6,000 48 Weeks 3,000
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    Mouser Electronics DXTN10060DFJBWQ-7 2,705
    • 1 $0.90
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    Newark () DXTN10060DFJBWQ-7 Tape & Reel 100
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    DXTN10060DFJBWQ-7 Cut Tape 5
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    Bristol Electronics DXTN10060DFJBWQ-7 2,000
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    Avnet Asia DXTN10060DFJBWQ-7 42 Weeks 3,000
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    Avnet Silica DXTN10060DFJBWQ-7 42 Weeks 3,000
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    Diodes Incorporated DXTN10060DF-7

    PWR LOW SAT TRANSISTOR SOT23 T&R
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    DigiKey () DXTN10060DF-7 Digi-Reel 2,802 1
    • 1 $0.42
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    DXTN10060DF-7 Cut Tape 2,802 1
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    DXTN10060DF-7 Tape & Reel 2,802 3,000
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    Avnet Americas DXTN10060DF-7 Tape & Reel 40 Weeks 3,000
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    Mouser Electronics DXTN10060DF-7
    • 1 $0.69
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    • 100 $0.28
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    SMC CYLINDERS CY3B32TN-1006

    CYLINDER, RODLESS, MAGNETICALLY COUPLED, CY3 SERIES
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    RS CY3B32TN-1006 Bulk 5 Weeks 1
    • 1 $666.88
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    SMC CYLINDERS RZQL63TN-100-6

    CYLINDER, 3-POSITION, RZQ SERIES
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    RS RZQL63TN-100-6 Bulk 5 Weeks 1
    • 1 $475.12
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    TN1006 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Contextual Info: Maximize ispMACH 5000VG and ispLSI 5000VE Functionality with Dual-OR Macrocells July 2001 Technical Note TN1006 Introduction Coming close to the macrocell limit? Why not double the number of functions used by your dual-OR output capability of the macrocells. This applications note shows two ways to implement the dual-OR function in the I/O architecture. The first method locks pins and signals to the same macrocell, and the second method groups signals


    Original     		5000VG 5000VE TN1006 PDF