TN0514 Search Results
TN0514 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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MS-026
Abstract: MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512L18P MT55L512V18P
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mt55l512l18pmt55l512v18pmt55l256l32pmt55l256v32p+6 | |
MT55L256L18P1T-10A
Abstract: MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal
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mt55l256l18p1mt55l256v18p1mt55l128l32p1mt55l128v32p1+9 | |
MT58L64L36P
Abstract: MS-026 MT58L128L18P MT58L128V18P MT58L64L32P MT58L64V32P MT58L64V36P
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mt58l128l18pmt58l64l32pmt58l64l36pmt58l128v18p+7 | |
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Contextual Info: SRAM ADDENDUM Attention: Micron has discontinued its 119-pin BGA SRAM package. While we are currently working to update these data sheets, please note that this data sheet still shows the discontinued package. For further information please call 208-368-3900. |
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119-pinmt55l512l18f | |
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Contextual Info: 1Mb: 64K x 18, 32K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 1Mb SYNCBURST SRAM MT58L64L18D, MT58L32L32D, MT58L32L36D 3.3V VDD, 3.3V I/O, Pipelined, DoubleCycle Deselect FEATURES • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply VDD |
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mt58l64l18dmt58l32l32dmt58l32l36d | |
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Contextual Info: 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM 8Mb SYNCBURST SRAM MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through FEATURES • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply VDD |
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mt58l512l18fmt58l256l32fmt58l256l36fmt58l512v18f+6 | |
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Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation |
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mt54v512h18e512kx18 | |
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Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE |
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mt54v512h18a165-pin | |
zbt sram 1994Contextual Info: SRAM ADDENDUM Attention: Micron has discontinued its 119-pin BGA SRAM package. While we are currently working to update these data sheets, please note that this data sheet still shows the discontinued package. For further information please call 208-368-3900. |
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119-pinmt55l256l18f1mt55l128l32f1mt55l128l36f1+4 | |
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Contextual Info: ADVANCE 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH ZBT SRAM MT55L512L18F, MT55L256L32F, MT55L256L36F; MT55L512V18F, MT55L256V32F, MT55L256V36F 8Mb ZBT SRAM 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • |
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mt55l512l18fmt55l256l32fmt55l256l36fmt55l512v18f+2 | |
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Contextual Info: 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation |
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mt57v256h36p165-ball | |
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Contextual Info: PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 4Mb ZBT SRAM MT55L256L18F1, MT55L128L32F1, MT55L128L36F1; MT55L256V18F1, MT55L128V32F1, MT55L128V36F1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • |
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august/7/00165-pinmt55l256l18f1 | |
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Contextual Info: ADVANCE‡ 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Pin FBGA Fast cycle times: 3.3ns, 4ns, 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation |
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mt57v256h36p | |
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Contextual Info: 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM 8Mb SYNCBURST SRAM MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through FEATURES • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply VDD |
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100-pin165-pin119-pinjuly/18/00+2 | |
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4c 8184
Abstract: BGA 2J marking code 18-SE
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apr/6/00jan/18/00119-pinnov/11/99+4 | |
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Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE |
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mt54v512h18a | |
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Contextual Info: ADVANCE‡ 0.13µm Process 36Mb: 2 MEG x 18, 1 MEG x 32/36 PIPELINED ZBT SRAM 36Mb ZBT SRAM MT55L2MY18P, MT55V2MV18P, MT55L1MY32P, MT55V1MV32P, MT55L1MY36P, MT55V1MV36P 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O Features Figure 1: 100-Pin TQFP • High frequency and 100 percent bus utilization |
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mt55l2my18p165-ball | |
BW35Contextual Info: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDRIIb4 SRAM 36Mb DDRII CIO SRAM 4-WORD BURST MT57W4MH8J MT57W4MH9J MT57W2MH18J MT57W1MH36J FEATURES • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA |
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mt57w1mh36jbw35 | |
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Contextual Info: NOT RECOMMENDED FOR NEW DESIGNS 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 18Mb SYNCBURST SRAM MT58L1MY18P, MT58V1MV18P, MT58L512Y32P, MT58V512V32P, MT58L512Y36P, MT58V512V36P 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O, Pipelined, Single-Cycle Deselect |
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apr/6/00jan/18/00nov/11/99mt58l1my18p | |
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Contextual Info: PRELIMINARY‡ 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDR SIO SRAM 18Mb DDR SIO SRAM 2-WORD BURST MT57W2MH8C MT57W1MH18C MT57W512H36C FEATURES • • • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement |
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mt57w1mh18c | |
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Contextual Info: 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM 8Mb SYNCBURST SRAM MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through FEATURES • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply VDD |
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100-pin165-pin119-pinmt58l512l18f | |
MT58L128L32Contextual Info: 4Mb: 256K x 18, 128K x 32/36 PIPELINED, SCD SYNCBURST SRAM 4Mb SYNCBURST SRAM MT58L256L18P1, MT58L128L32P1, MT58L128L36P1; MT58L256V18P1, MT58L128V32P1, MT58L128V36P1 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle Deselect FEATURES 100-PIN TQFP1 • Fast clock and OE# access times |
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165-pin100-pin119-pinmt58l256l18p1+1 | |
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Contextual Info: 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM 2Mb ZBT SRAM MT55L128L18P1, MT55L64L32P1, MT55L64L36P1 3.3V VDD, 3.3V I/O FEATURES • • • • • • • • • • • • • • • • • • • High frequency and 100 percent bus utilization |
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june/21/00x32/36165-pinmay/23/00+1 | |
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Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation |
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512kx18mt54v512h18e | |