TIOC Search Results

OSC1 1

Contextual Info: 1.2 Internal Block Diagram Port A Port B Port C WDT x 2 channels PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Port 3 ROM mask ROM, flash memory PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3

Contextual Info: Internal Block Diagram PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VCL VCL VCC VCC VCC VSS VSS VSS 1.2 Port A Port B PB7/TIOCB5/PWOB PB6/TIOCA5/PWOA PB5/TIOCB4/PVOB PB4/TIOCA4/PVOA PB3/TIOCD3/PUOB PB2/TIOCC3/PUOA PB1/TIOCB3/PCO PB0/TIOCA3/ Port C WDT 1 channel PA3/SCK2/

3 phase

Abstract: SH7144
Contextual Info: APPLICATION NOTE SH7144/45 Group Positive-Phase/Negative Phase PWM 3-Phase Output 1. Specifications φ Pulse period Pulse high width Pulse low width TIOC3B pin TIOC3D pin Pulse low width TIOC4A pin Pulse high width TIOC4C pin TIOC4B pin Pulse low width Pulse high width

71P26

Abstract: tmci1
Contextual Info: XTAL VCC STBY NMI RES MD2 WDTOVF FWE* P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF7/ø 69 65 PF6/AS 70 66 PF5/RD 71 VSS PF4/HWR 72 EXTAL PF3/LWR/IRQ3 73 67 PF2/WAIT/IRQ2/BREQO

Contextual Info: WDTOVF FWE, EMLE * P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 59 58 57 56 55 54 53 52 51 MD2 60 RES 61 66 NMI XTAL 67 62 EXTAL 68 63 VSS 69 VCC PF7/ø 70 STBY PF6/AS 71 64 PF5/RD 72 65 PF3/LWR/IRQ3 PF4/HWR 73 PF1/BACK/IRQ1/CS5

AN11

Contextual Info: 1.3 Pin Description 1.3.1 Pin Arrangement 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Top view FP-100B P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD

SH7034

Contextual Info: PA8/BREQ VSS PA7/BACK PA6/RD PA5/WRH LBS PA4/WRL (WR) 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 Top view (FP-112) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PA3/CS7/WAIT PA2/CS6/TIOCB0

H8S/2623

Abstract: H8S/2626
Contextual Info: 1.2 Internal Block Diagram Port A WDT x 1 channel Port B ROM Mask ROM, flash memory*1 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C Peripheral data bus PC break controller (2 channels)

h927

Abstract: C34F F030 F031 F040
Contextual Info: APPLICATION NOTE H8/300H SLP Series PWM Output Using TPU Synchronous Operation Function Introduction The synchronous operation function of the 16-bit timer pulse unit TPU is used to output 2-phase PWM waveforms from the TGRA_1 PWM output pin (TIOCA1) and TGRA_2 PWM output pin (TIOCA2).

pulse generator

Abstract: pd3 controller
Contextual Info: 1.2 Internal Block Diagram Port A Port B 8-bit timer 4 channels ROM Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 WDT1 (subclock) Port C WDT0 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3

2227 diagram

Abstract: bus pc
Contextual Info: 1.2 Internal Block Diagrams Port A PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Port B PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2 /A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2

PUOA

Abstract: QFP-80
Contextual Info: • Compact package Package Code Body Size QFP-80 FP-80A 14.0 x 14.0mm 0.65mm PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Internal Block Diagram VCL VCL VCC VCC VCC VSS VSS VSS 1.2 Pin Pitch Port A WDT 1 channel Port B ROM (Mask ROM, flash memory*1) PB7/TIOCB5/PWOB

AN1338

Contextual Info: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PA1/POE1/TXD2 VcL PA0/POE0/RXD2 Vss FWP Vcc RES NMI MD3 MD2 MD1 MD0 EXTAL XTAL PLLVcL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RXD3 PE5/TIOC1B/TXD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RXD2

H8S-2398

Abstract: h8s 2352 TFP-120 H8S-2357 FP120
Contextual Info: 1.3 Pin Description 1.3.1 Pin Arrangement P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 90 89 88 87 86

Contextual Info: 1.2 Internal Block Diagrams Port A 8-bit timer 4 channels ROM Port F PF7/ø PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/ WAIT PF1/ BACK/BUZZ PF0/BREQ/IRQ2 WDT1 (subclock operation) Port B WDT0 Port C PC break controller (2 channels) PB7 / A15/TIOCB5 PB6 / A14/TIOCA5

m9630

Abstract: AN10 AN11 AN12 AN13 AN14 AN15 LQFP-100 up 6261 POEI
Contextual Info: 03^>>>><>>>><>>zzzzzz5^^^ nnnnnnnnnnnnnnnnnnnnnnnnn TI -<| O O -* ro t f I > f f i 0 ' l 5 C c 0 - ‘ M W J > V i S O-^O Vss PE21/TIOC4DS Vcc PE20/TIOC4CS PE19/RD/TIQC4BS PE18/CST/TI0C4AS PEl7yCSO/TIOC3DS PE16/WAIT/TIOC3BS PE15/TIOC4Dy RQOUT PE14/TIOC4C

Contextual Info: 1.2 Internal Block Diagram Port A Port B PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/ A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7/PWM1 PC6/A6/PWM0 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 14-bit PWM timer Port 3 8bit timer x 4 channels

h8s 2238

Abstract: cs471
Contextual Info: 1.2 Internal Block Diagrams Port A 8-bit timer 4 channels ROM Port F PF7 / ø PF6 /AS PF5 /RD PF4 /HWR PF3 /LWR/ADTRG/IRQ3 PF2 / WAIT PF1 / BACK/BUZZ PF0 /BREQ/IRQ2 WDT1 (subclock operation) Port B WDT0 Port C PC break controller (2 channels) PB7 / A15/TIOCB5

po14

Contextual Info: 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 /TMRI0 P23 /PO3 /TIOCD3 /TMCI0 P24 /PO4 /TIOCA4 /TMRI1 P25 /PO5 /TIOCB4 /TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1

Contextual Info: 1.3 Pin Description 1.3.1 Pin Arrangement 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB

three phase three level inverter

Abstract: PM15CSJ060
Contextual Info: mmnsL PM15CSJ060 Powerex, Inc., 200 Hillis Street, Youngwood, Pennsylvania 15697-1800 724 925-7272 IntBlU/TIOCt ModUlB Three Phase IGBT Inverter Output 15 Amperes/600Volts 1. V upc 2. UFo 3. U p 4. V upi 5. V v p c 6. V Fo 7. V p 8. V vpi 9. V w pc 10 W Fo

F-ZTAT

Abstract: an3845
Contextual Info: XTAL VCC STBY NMI RES MD2 WDTOVF FWE, EMLE, VCL * P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF7/φ 66 PF6/AS 69 VSS PF5/RD 70 EXTAL PF4/HWR 71 67 PF3/LWR/IRQ3 72 68

Contextual Info: 1.2 Internal Block Diagram Port A WDT x 1 channel Port B ROM Mask ROM, flash memory*1 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C Peripheral data bus PC break controller (2 channels)

F030

Abstract: F040 F046
Contextual Info: APPLICATION NOTE H8/300H SLP Series Pulse Cycle Measurement Using TPU Input Capture Function Introduction The input capture function of the 16-bit timer pulse unit TPU is used to measure the time (cycle) from the rising edge of a pulse input from an input capture input pin (TIOCA1) to the next rising edge.