TECNOLOGY OF CONTROL Search Results

Contextual Info: 3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER FEATURES: ing advanced dual metal CMOS tecnology. The device is con­ figured with fan out of four use in high speed synchronous memory applications. The ALVCH16x345 is ideal for driving memory modules in systems where multiple memory modules are used. I each of

Contextual Info: 3.3V FAST CMOS REGISTERED AD DRESS LINE DRIVER IDT74ALVCH1 6345 ADVANCE INFORMATION FEATURES: DESCRIPTION: • C o m m o n feat ur es: The ALVCH16345 is a registered address driver built using advanced dual metal CMOS tecnology. The device is config­ ured with fan out of four use in high speed synchronous

buffer cmos 1.8V

Abstract: idt 20 PIN SOIC CMOS TTL fan IN and fan OUT
Contextual Info: ADVANCED TIMING SOLUTIONS FAN OUT BUFFERS Fan Out Buffers IN 01 02 03 04 05 06 07 08 09 010 Control Logic Fan Out Buffers are designed for high-speed clock distribution where signal quality and skew are critical. The buffers can also allow single point-to-point

NJU7250

Abstract: NJU7250F NJU7250F25 NJU7250F27 NJU7250F28 NJU7250F29 NJU7250F30 NJU7250F32 NJU7250F33
Contextual Info: NJU7250 Low Dropout Voltage Regulator „ GENERAL DESCRIPTION The NJU7250 series is low dropout voltage and high precision positive voltage regulator with ON/OFF control. This IC is suitable for the battery items because of low operating current and 150mA output current.

Contextual Info: NJU7250 Low Dropout Voltage Regulator ̈ GENERAL DESCRIPTION The NJU7250 series is low dropout voltage and high precision positive voltage regulator with ON/OFF control. This IC is suitable for the battery items because of low operating current and 150mA output current.

Contextual Info: ADVANCED TIMING SOLUTIONS PROGRAMMABLE SKEW PLLS Programmable Skew PLLs What are Programmable Skew PLLs? Signal analysis at target device ASIC Clk out Clk out FIFO input w/o adjusted skew. Ref Clk out 1 CPU Clk out Turboclk Clk out Ref Clk Clk out 2 Clk

Contextual Info: Monitoring Relays Surge Arresters for PV system Type DSF D • Type 2 class C according to EN61643-11 (VDE 0675, part 6-11) • Approved UL1449 3rd Edition • Complies with IEC-61643-1, VTE C 61-740-51 • Do not require backup fuse up to 200kArms (UL 1449 3rd Ed.)

reset technique

Contextual Info: STSR2 FORWARD SYNCHRONOUS RECTIFIERS SMART DRIVER ADVANCE DATA • ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V ADVANCED FAST BI-CMOS TECNOLOGY TYPICAL PEAK OUTPUT CURRENT: SOURCE -2.5A, SINK 4A OPERATING FREQUENCY: 50 TO 750 KHz LOW QUIESCENT CURRENT: 1.5 mA

Contextual Info: T835-600G T850-600G HIGH PERFORMANCE TRIAC FEATURES HIGH COMMUTATION PREFORMANCES SNUBBERLESS TECHNOLOGY HIGH NOISE IMMUNITY dV/dt HIGH It s m DESCRIPTION The T835-600G and T850-600G triacs are using high performance SNUBBERLESS technology. They are intended for AC control applications

Contextual Info: B5S162862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL AND 25Ω SERIES RESISTOR IN OUTPUT PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 1.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 25Ω (TYP) at VCC = 5.0V TA=25°C

B5S16862

Abstract: B5S16862TTR TSSOP48
Contextual Info: B5S16862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 5Ω (TYP) at VCC = 5.0V TA=25°C LOW POWER DISSIPATION:

Contextual Info: 74B5S162862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL AND 25Ω SERIES RESISTOR IN OUTPUT PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 1.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 25Ω (TYP) at VCC = 5.0V TA=25°C

B5S162861TTR

Abstract: B5S162862 TSSOP48
Contextual Info: B5S162862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL AND 25Ω SERIES RESISTOR IN OUTPUT PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 1.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 25Ω (TYP) at VCC = 5.0V TA=25°C

n094

Contextual Info: 74B5S16862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 5Ω (TYP) at VCC = 5.0V TA=25°C LOW POWER DISSIPATION:

B5S16862

Abstract: B5S16862TTR TSSOP48
Contextual Info: B5S16862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 5Ω (TYP) at VCC = 5.0V TA=25°C LOW POWER DISSIPATION:

16862

Abstract: B5S162861TTR B5S162862 TSSOP48
Contextual Info: B5S162862 20-BIT TWO PORT BUS SWITCH WITH FOUR ENABLE CONTROL AND 25Ω SERIES RESISTOR IN OUTPUT PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 1.25ns MAX. at VCC = 4.5V TA=85°C ON RESISTANCE BETWEEN TWO PORT: 25Ω (TYP) at VCC = 5.0V TA=25°C

oki marking

Abstract: DEVICE MARKING CODE table oki LOT NUMBER marking LINEAR MARKING OKI marking code list bk marking linear marking code Mos MARKING CODE 06 markings marking P 16
Contextual Info: This version: Apr. 2001 Previous version:Jun. 1997 PACKAGE INFORMATION 6. MARKINGS This document is Chapter 6 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 6. MARKINGS 6. MARKINGS There are two kinds of marking layout; “standard marking layout” that is specified by Oki Electric and “special marking

SDIP24

Abstract: TDA7314
Contextual Info: TDA7314 DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESS PRODUCT PREVIEW 1 STEREO INPUT SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM LOUDNESS FUNCTION VOLUME CONTROL IN 1.25dB STEPS

TDA7314

Abstract: SDIP24 0890E S2C2 812A1
Contextual Info: TDA7314 DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESS 1 STEREO INPUT SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM LOUDNESS FUNCTION VOLUME CONTROL IN 1.25dB STEPS TREBLE AND BASS CONTROL

SDIP24

Abstract: TDA7314
Contextual Info: TDA7314  DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESS 1 STEREO INPUT SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM LOUDNESS FUNCTION VOLUME CONTROL IN 1.25dB STEPS TREBLE AND BASS CONTROL

Contextual Info: SIM-030ST Surface Mount High Output Infrared LEDs Absolute maximum ratings Ta=25°C Parameter Symbol Limits Unit IF 100 mA Forward current Reverse voltage VR 5 V Power dissipation PD 180 mW Operating temperature Topr −25~＋85 °C Storage temperature

Contextual Info: SIM-040ST Surface Mount High Output Infrared LEDs Absolute maximum ratings Ta=25°C Parameter Symbol Limits Unit IF 100 mA Forward current Reverse voltage VR 5 V Power dissipation PD 180 mW Operating temperature Topr −25 to＋85 °C Storage temperature

loudness control

Abstract: stereo volume tone bass treble loudness control circuit Hi-fi stereo audio processor tecnology of control SDIP24 TDA7314 S2C2
Contextual Info: TDA7314 DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESS PRODUCT PREVIEW 1 STEREO INPUT SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM LOUDNESS FUNCTION VOLUME CONTROL IN 1.25dB STEPS

23732

Abstract: MINT1500 MINT1500A4814E01 MINT1400A MINT1500A1214E01 GNT448ABG
Contextual Info: 937-2012.qxp:QuarkCatalogTempNew 8/29/12 11:57 AM Page 937 10 Medical Switching Power Supplies Dimensions: L x W × H 7" × 3.3" × 1.5" For 1U Applications Up to 500 W of AC-DC Power Universal Input: 85-264 VAC Class I Input Standby and Fan Output Voltages