TEA 1601 Search Results

LSI2032

Abstract: SBC5206 74FCT16245 MCM32 VinC26 27C080 D24-D25 pd446 J42C27 TL7705ACP
Contextual Info: SP7 9x4.7K +5 1 +5 SP4 2 3 4 5 6 7 8 910 9x4.7K +5 1 A[0.27] 2 3 4 5 6 7 8 910 160150 140128118110 102 94 86 77 6960 52 44 36 3024 1812 59 -RESET 62 63 64 -IRQ7 -IRQ4 -IRQ1 66 67 68 -BR -BD -BG 127 126 125 121 122 124 -BKPT DSI -HIZ DSCLK TCK DSO 159 158

A42 B331

Abstract: CA91C860B-40IQ CA91C860B-40CQ CA91C860B-50CQ tea 1601 t CA91C860B a44 b331 CA91C860 T337A CA91L860B-50CE
Contextual Info: QSpan CA91C860B, CA91L860B PCI to Motorola Processor Bridge Manual http://www.tundra.com The information in this document is subject to change without notice and should not be construed as a commitment by Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra

TEA 1112 A

Abstract: TCS101
Contextual Info: Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Features — tco = 4 .5 ns • Product-term clocking • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

TSPC860

Abstract: microprocessor PC860SR
Contextual Info: TSPC860 Integrated Communication Processor Datasheet Features • PowerPC Single Issue Integer Core • Precise Exception Model • Extensive System Development Support • • • • • • • • • • • – On-chip Watchpoints and Breakpoints – Program Flow Tracking

ts68EN360

Abstract: we3 marking
Contextual Info: TSPC860 Integrated Communication Processor Datasheet Features • PowerPC Single Issue Integer Core • Precise Exception Model • Extensive System Development Support • • • • • • • • • • • – On-chip Watchpoints and Breakpoints – Program Flow Tracking

Contextual Info: IDT Tsi620 RapidIO Switch / RapidIO-to-PCI Bridge  User Reference Manual June 4, 2013 Formal Status GENERAL DISCLAIMER Integrated Device Technology, Inc. "IDT" reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or

Ericsson TSR 491 628

Abstract: NT 1307c ericsson TSR 491 641 Ericsson nokia 1600 schematic diagram schematic diagram UPS active power 600 schematic diagram UPS 600 Power free marking code H02 schematic diagram UPS active power 400 tsi620-10gclv
Contextual Info: Tsi620 RapidIO Switch / RapidIO-to-PCI Bridge User Manual Preliminary October 2007 80D7000_MA001_02 Titlepage Trademarks TUNDRA is a registered trademark of Tundra Semiconductor Corporation Canada, U.S., and U.K. . TUNDRA, the Tundra logo, Tsi620, and Silicon Behind the Network, are trademarks of Tundra Semiconductor Corporation.

PC8265A

Abstract: microprocessor sp19b
Contextual Info: PC8265A PowerPC based Communications Processor PowerQUICC II Datasheet Features • PC603e Microprocessor Embedded PowerPC Core at 133 - 300 MHz • • • • • • • – 280 MIPS at 200 MHz (Dhrystone 2.1) – 520 MIPS at 300 MHz (Dhrystone 2.1)

PC8260A

Abstract: 8265A PC603E
Contextual Info: PC8265A/PC8260A Power Architecture based Communications Processor PowerQUICC II Datasheet Features • PC603e Microprocessor Embedded Power Architecture Core at 133 - 266 MHz • • • • • • • – 280 MIPS at 200 MHz (Dhrystone 2.1) – 520 MIPS at 300 MHz (Dhrystone 2.1)

TS68040

Abstract: microprocessor 5962-9314301MXA 5962-9314301MYC ATC 1184 296Bytes IF-FC2 CAPACITOR SMD 107C ts68030 TS68882
Contextual Info: TS68040 Third-Generation 32-bit Microprocessor Datasheet Features • • • • • • • • • • • • • • 26-42 MIPS Integer Performance 3.5-5.6 MFLOPS Floating-Point-Performance IEEE 754-Compatible FPU Independent Instruction and Data MMUs

TSPC603R

Abstract: microprocessor LNM80 DH21
Contextual Info: TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support

emcp

Abstract: JEDEC JESD51-8 BGA CI-CGA-255
Contextual Info: TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support

Contextual Info: ATV2500H/L Features • Third Generation Programmable Logic Structure Easily Achieves Gate Utilization Factors of 80 Percent • Increased Logic Flexibility 86 Inputs and 72 Sum Terms • Flexible Output Macrocell 48 Flip-Flops • 2 per Macrocell 3 Sum Terms - Can Be OP'ed and Shared

Tundra QSpan

Contextual Info: Manual d i i TUNDRA TDRAT>0 0&0 QSpan PCI to Motorola Processor Bridge Manual TUNDRA Summer 1997 http://www.tundra.com The information in this document is subject to change without notice and should not be construed as a commitment by Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra

PC8270

Contextual Info: PC8280/PC8270 Integrated Communication Processors Datasheet Features PC603e Microprocessor Embedded PowerPC Core at 166-450 MHz 603e Core with 16K Inst and 16K Data Caches 64-bit 60x Bus, 32-bit Local/PCI Bus 128K ROM, 32K IRAM, 32K DPRAM Three FCCs Supporting ATM, 10/100 Ethernet or HDLC

TMS 320 C 6X processor

Contextual Info: PC755BM8 RISC Microprocessor Multichip Package Datasheet - Preliminary Specification Features • • • • • • PC755BM8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz

0.13 um CMOS

Contextual Info: ATV2500H/L Features • Third Generation Programmable Logic Structure Easily Achieves Gate Utilization Factors of 80 Percent Increased Logic Flexibility 86 Inputs and 72 Sum Terms Flexible Output Macrocell 48 Flip-Flops - 2 per Macrocell 3 Sum Terms - Can Be OR’ed and Shared

G191053

Abstract: gcu 101 LC-R123R4PG LC-R123R4P EUROBAT TAG 034
Contextual Info: Individual Data Sheets LC-R123R4PG For main and standby power supplies. Expected trickle design life: 6 – 9 years at 20 °C according to Eurobat. VdS G191053 Dimensions mm 4.75 4.75 Battery case resin: standard (UL94HB) Duration of discharge vs Discharge current

Contextual Info: PC7447A PowerPC 7447A RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 3000 Dhrystone 2.1 MIPS at 1.3 GHz Selectable Bus Clock 30 CPU Bus Dividers up to 28x Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

PC7447A

Abstract: microprocessor LGA land pattern GBL 08 Bridge diode TT 2076 powerpc 7447a
Contextual Info: PC7447A PowerPC 7447A RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 3000 Dhrystone 2.1 MIPS at 1.3 GHz Selectable Bus Clock 30 CPU Bus Dividers up to 28x Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

Contextual Info: PRELIMINARY CY37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD Features — tpD = 10 ns — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — t Co = 6 .5 ns — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

0828H

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

ras 0610 relay

Abstract: relay sm1 SH7712 RBL 43 P 530 SE SH7710 S273S
Contextual Info: User's Manual 32 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7710, SH7712, SH7713 Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Contextual Info: CY37192 UltraLogic 192-Macrocell ISR™ CPLD Features — tco = 4 .5 ns • Product-term clocking • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes