TDC 723 Search Results

PC3200

Contextual Info: HD74CDCV857B 2.5-V Phase-lock Loop Clock Driver REJ03D0003-0301Z Previous ADE-205-723A (Z Rev.3.01 Apr.24.2003 Description The HD74CDCV857B is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.

ic 74151

Abstract: ic 74163 oki cross MSM92RB01 MSM92RB02 msm32r0120 oki 82c54 82C54 oki of ic 74151 30R06
Contextual Info: MSM30R0000/MSM32R0000/MSM92R000 Second-Generation 0.5µm Sea of Gates and Customer Structured Arrays DESCRIPTION Oki's second-generation 0.5µ m ASIC products are available in both Sea Of Gates SOG and Customer Structured Array (CSA) architectures. The MSM30R Series, MSM32R Series, and MSM92R Series all offer

82C54 oki

Abstract: ic 74151 RB35 ic 74151 specification ic 74163 oki 82c54 oki cross MSM92RB01 MSM92RB02 rb19
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MSM30R/32R/92R 0.5µm Sea Of Gates and Customer Structured Arrays July 2001 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

82C54 oki

Abstract: ic 74151 oki 82c54 OKI SEMICONDUCTOR RB35 ic 74151 specification oki cross MSM92RB01 MSM92RB02
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MSM30R/32R/92R 0.5µm Sea Of Gates and Customer Structured Arrays August 2002 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

Contextual Info: Gl CH9088 CHRONTEL PCI Clock Generator with Buffers Features Description • Generates preset CPU and PCI frequencies, 1 peripheral clock, and buffers the input reference frequency CH9088 is a triple PLL clock generator designed for high performance computer motherboards. CH9088

CH9088A

Abstract: TDC 723 CH9088
Contextual Info: CH9088 CHRONTEL PCI Clock Generator with Buffers Features Description • Generates preset CPU and PCI frequencies, 1 peripheral clock, and buffers the input reference frequency CH9088 is a triple PLL clock generator designed for high performance computer motherboards. CH9088

Z8420A

Abstract: Z80A PIO zilog Z8420 z80a-PIO z80pio centrifuge machine for acceleration
Contextual Info: Z 8420 Military Z80 PIO Parallel Input/Output Controller Military Electrical Specification 17: 1 July 1985 FEATURES • Provides a direct interface between Z80 microcomputer systems and peripheral devices. ■ Two ports with interrupt-driven handshake for fast

NE8392CN

Abstract: heartbeat IN916 NE8392C NE8392CA AC DC transformer Philips ethernet serial converter "network interface controller"
Contextual Info: • bbSa^EM OCHMbMS 3S7 * S I C 3 Philips Semiconductors Data Communications Products Product specification Coaxial transceiver interface for Ethernet/Thin Ethernet DESCRIPTION NE8392C PIN CONFIGURATION The NE8392C Coaxial Transceiver Interface CTI is a coaxial line

TXO-210

Abstract: E839
Contextual Info: Philips Sem iconductors Data C om m unications Products Product specification Coaxial transceiver interface for Ethernet/Thin Ethernet DESCRIPTION NE8392C PIN CONFIGURATION The NE8392C Coaxial Transceiver interface CT! is a coaxial line driver/receiver for Ethernet (10base5) and Thin Ethernet (10base2)

DS1623S

Abstract: DS1623 S1623
Contextual Info: PRELIMINARY DALLAS s e m ic o n d u c t o r DS1623 D îQ itâl T h G rm o m G tG r a n d T h G rm o s ts t PIN ASSIGNMENT FEATURES • Requires no external components 1 8 2 7 -2-I t high RST Q E 3 GND • Temperature is read as a 9-bit value cm 4 6 3D 5 ^

Contextual Info: b4E D „ • 75=i73bG RAYTHEON/ GGQfiHbl T1Ì IRTN SEMICONDUCTOR TDC1012 TDC1016 Video Speed D/A Converter D A 10-Bit, 20 Msps Description Features T h e T D C 1 0 1 6 is a bipolar monolithic digital-to-analog converter which can convert digital data into an analog

rdc 2882

Abstract: TS3DD
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145532 Advance Information ADPCM T ran s c o d er DW SUFFIX SOG CASE 751G Conforms to G.721-1988 and T1.301-1987 The MC145532 Adaptive Differential Pulse Code Modulation ADPCM Transcoder provides a low-cost, full-duplex, single-channel transcoder to (from)

MC145532DW

Abstract: MC145532 MC145480 MC145503 MC145532L MC145557 NP470
Contextual Info: MOTOROLA Order this document by MC145532/D SEMICONDUCTOR TECHNICAL DATA MC145532 ADPCM Transcoder Conforms to G.721–1988 and T1.301–1987 The MC145532 Adaptive Differential Pulse Code Modulation ADPCM Transcoder provides a low–cost, full–duplex, single–channel transcoder to

dma 8257

Abstract: BPK-72 Bubble Memory IC AN 7220 Bubble Memory BPK72 Memtech intel 8257 7220 DMA Controller 8257 IC AN 7220 b
Contextual Info: M em /e c h 7220 CONTROLLER FOR 1 MBIT BPK 70 AZ BUBBLE MEMORY SUBSYSTEM 0°C To 75°C —20°C To + 85°C —40°C To +85°C 7220-1 7220-5 7220-6 • Provides Interface between Host Microprocessor and 1 Mbit Bubble Subsystems ■ 16 Easy-to-Use Commands ■ Interfaces to 8080/85/86/88/186/286

565 PLL

Abstract: cash box guard with procedure minor project TWO BANDS v.32 Modem Chips radioshack MCP 42010 MIc TMR 9202 atmel bootloader tutorial DSP56F826 DSP56F827 matlab g.711
Contextual Info: Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Embedded SDK Software Development Kit Targeting Motorola DSP56F826/827 Platform SDK127/D Rev. 5, 03/20/2003

MC14499P application note

Abstract: wiring diagram audio amplifier ic 6283 era 555 MOTOROLA delta dvp plc communication cable wiring diagram siemens transistor manual 68000 MC68681 PROGRAMMING EXAMPLE DSP56200 SP5615 CORDED MOTOROLA CT2 Solid State Optoelectronics Data Book 1977
Contextual Info: Selection Guides Data Sheets Evaluation Kits Application Notes and Product Literature Glossary Handling and Design Guidelines Quality and Reliability Mechanical Data DATA CLASSIFICATION Product Preview This heading on a data sheet indicates that the device is in the formative stages or under

EIT30

Abstract: 29C93
Contextual Info: T e m ic 29C98 MATRA MHS B-Channel Resynchronizer Description ISDN public networks CENTRAL OFFICES usually implement channel switching except on leased lines. When higher data rates than 64 kbps are required between two terminals or between a terminal and a

Contextual Info: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

X9009

Abstract: r13-112 switch XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 X-9009 XC5215
Contextual Info: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

AS 108-120

Abstract: LC1 D12 10 K1882 nec d 882 p datasheet XAPP 138 data XC5200 XC3000 XC4000 XC5202 XC5204
Contextual Info: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

LC1 D18 wiring diagram

Abstract: 8165 input chip chart XC520 XC5200 Family XC5202 XC5204 XC5206 XC5210 XC5215 XC3000
Contextual Info: Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology

Z80h

Abstract: TDA 718 z80b 74LS74 timing diagram Z80B-CPU Z850 74ls74 timing setup hold z80a cpu Z850D 74LS164M
Contextual Info: A p p l ic a t io n N o t e <£ZiI£3G INTERFACING Z80 CPUS TO THE Z8500 P e rip h e ra l fa m ily INTRODUCTION Data Bus Signals The Z8500 Family consists of universal peripherals that can interface to a variety of microprocessor systems that use a non-multiplexed address and

Contextual Info: RT8877C Dual-Output PWM Controller for AMD SVI2 CPU Power Supply General Description Features The RT8877C is a 4 + 2 phases PWM controller. Moreover, it is compliant with AMD SVI2 Voltage Regulator Specification to support both CPU core VDD and Northbridge portion of the CPU (VDDNB). The RT8877C

a103 636 transistor

Abstract: MIPS32 cache LSI Rapidchip K9CFG CFG102 ARM926 ARM926EJ-S DB04-000094-02 Preliminary Gflx-r RapidChip Cell Technology Data infiniband PHY
Contextual Info: DATASHEET RapidChip Integrator Platform ASIC Family July 2004 Preliminary DB08-000237-02 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using