TCA 210 Search Results

Contextual Info: intel ~ ¡SM001DR09P 9-CHIP 1M x 9 (1,048,576 x 9) DYNAMIC RAM MEMORY MODULE WITH FAST PAGE MODE *4 (Formerly Known as 21019) m Performance Range 1 o ÌSM001DR09P 1 Parameter CO Symbol Units tRAC Access Tim e from RAS 70 80 ns tcA C Access Tim e from CAS

Contextual Info: KM41C16000A/AL/ALL/ASL CMOS DRAM 16M x 1 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION T h e S a m s u n g K M 4 1 C 1 6 00 0 A /A L 7 A L L7 A S L is a high • Performance range: tRAC tCA C KM41C16000A/AL/ALL'ASL-5 50ns 13ns 90ns

TCA 210

Abstract: advanced tca LMU12GC20 LMU12GC35 MPY012H
Contextual Info: LMU12 LMU12 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ DESCRIPTION 20 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY012H Two’s Complement, Unsigned, or

TCA 210

Abstract: LMU12GC45 LMU12DC65 LMU12GC20 LMU12GC35 LMU12GC65 MPY012H
Contextual Info: LMU12 LMU12 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ DESCRIPTION 20 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY012H Two’s Complement, Unsigned, or

MSP50C30

Abstract: MSP50C34 bc 338-25 equivalent SPSU012 PSA B21 TSP50C30
Contextual Info: MSP50C30 MixedĆSignal Processor User’s Guide 2000 Mixed-Signal Products SPSU012A IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest

108F00

Abstract: tca 335 A MSP50C30 psa 200 53 TAM bra 94 SPSU012 TSP50C30 SPSS021
Contextual Info: MSP50C30 Mixed-Signal Processor User’s Guide SPSU012 NOVEMBER 1998 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

Contextual Info: LMU12 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES DESCRIPTION □ 20 ns Worst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY012H □ Two's Complement, Unsigned, or Mixed Operands □ Three-State Outputs □ Available 100% Screened to

Contextual Info: LMLL12 •Vi» /lif iu LMU12 mm 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES_ □ □ □ □ 20 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY012H Two's Complement, Unsigned, or Mixed Operands □ Three-State Outputs

Contextual Info: LMU12 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES □ □ □ □ DESCRIPTION 35 ns Worst-Case M ultiply Time Low Pow er CMOS Technology Replaces TRW MFY012H T w o's C om plem ent Unsigned, or Mixed O perands □ Three-State O utputs □ Available 100% Screened to

TH2074.5-A

Abstract: TH2028.5A TbA 2025 PP20012HSABBN5A PP15012HSABBN5A PP10012HSABBN5A TBA 129 ST8050C-1.5A trafo ct FTF7293HS-10-2-4.5-A
Contextual Info: Current transformers Measurement devices Three-phase CT trafo_077_b_1_cat trafo_010_a_1_cat trafo_108_a_1_cat NEW trafo_012_a_1_cat ÂÂ Energy efficiency appli_294_a Class 0.2s We offer class 0.2s for your energy efficiency or MID applications. Measurement devices

Contextual Info: LMU12 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ □ □ □ 20 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY012H Two's Complement, Unsigned, or Mixed Operands □ Three-State Outputs

Contextual Info: Lg G lc LMU12 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES D E S C R IP T IO N □ 35 ns Worst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY012H □ Two's Complement, Unsigned, or Mixed Operands □ Three-State Outputs

2A1121

Contextual Info: LMU12 12 x 12-bit Parallel Multiplier FEATURES DESCRIPTION □ □ □ □ 20 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY012H Two’s Complement, Unsigned, or Mixed Operands □ Three-State Outputs □ Available 100% Screened to

Contextual Info: LMU12 12 x 12-bit P a ra ll el M u l t ip l ie r DFVICES IN C O R P O H ArFTj FEATURES DESCRIPTION □ 35 n s W orst-C ase M ultiply Tim e □ L ow P ow er CM O S T echnology □ R eplaces TRW MPY012H □ T w o 's C om plem ent, U nsigned, or M ixed O p e ran d s

Contextual Info: TLK3104SA QUAD 3.125 Gbps SERIAL TRANSCEIVER SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001 D Quad 3.125 Gbps per Channel Transceiver D D D D D D D D Providing 10 Gbps Data Throughput Selectable Synchronized or Independent Channel Operation Selectable Transmitter Only, Receiver Only,

Contextual Info: TLK3104SA QUAD 3.125 Gbps SERIAL TRANSCEIVER SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001 D Quad 3.125 Gbps per Channel Transceiver D D D D D D D D Providing 10 Gbps Data Throughput Selectable Synchronized or Independent Channel Operation Selectable Transmitter Only, Receiver Only,

Contextual Info: TLK3104SA QUAD 3.125 Gbps SERIAL TRANSCEIVER SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001 D Quad 3.125 Gbps per Channel Transceiver D D D D D D D D Providing 10 Gbps Data Throughput Selectable Synchronized or Independent Channel Operation Selectable Transmitter Only, Receiver Only,

HM514100

Contextual Info: HM514100L Series Low Power Version 4,194,304-Word x 1-Bit Dynamic Random Access Memory • DESCRIPTION HM514100UP Series The Hitachi HM514100 is a CMOS dynamic RAM organized 4,194,304 word x 1-bit. HM514100 has realized high density, higher performance and various func­

P802

Abstract: TLK3104SA TLK3104SAGNT
Contextual Info: TLK3104SA QUAD 3.125 Gbps SERIAL TRANSCEIVER SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001 D Quad 3.125 Gbps per Channel Transceiver D D D D D D D D Providing 10 Gbps Data Throughput Selectable Synchronized or Independent Channel Operation Selectable Transmitter Only, Receiver Only,

Contextual Info: TLK3104SA QUAD 3.125 Gbps SERIAL TRANSCEIVER SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001 D Quad 3.125 Gbps per Channel Transceiver D D D D D D D D Providing 10 Gbps Data Throughput Selectable Synchronized or Independent Channel Operation Selectable Transmitter Only, Receiver Only,

Contextual Info: GOLDSTAR TECHNOLOGY IN C / 47E ]> • 402Ô7S7 GoldStar 1 «GST 0003433 TWé-23-/5 G M 7 1 C 4 1 0 0 A /A L 4,194,304 WORDSxl BIT CMOS DYNAMIC RAM Description Features The GM71C4100A/AL is the new generation dy­ namic RAM organized 4,194,304 x 1 Bit. GM71C4100A/AL has realized higher density, higher per­

TI BINARY DATE CODE

Abstract: BQ20Z80-V101 BQ2940
Contextual Info: bq20z80-V101 www.ti.com SLUS625C – SEPTEMBER 2004 – REVISED JULY 2005 SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK TECHNOLOGY FOR USE WITH THE bq29312 FEATURES • • • • • • • • • • • • • • • Patented Impedance Track™ Technology

stm cl-30

Abstract: TCA 700 v atm header error checking ATM timing diagram BIP-8 TCA 700 optical input to rca output circuit PFE 210 Aps 92 CY7C955
Contextual Info: 1CY 7C95 5 PRELIMINARY CY7C955 AX ATM-SONET/SDH Transceiver Features — Line Far End Receive Failure • WAN and LAN ATM physical layer device • Provides complete physical layer transport of ATM cells at — STS−3c/ STM−1 rate of 155.52 MHz — STS−1 rate of 51.84M Hz

Power Meter PM5350

Abstract: A558-5999-00 969489 SATURN 0X00 PM5350 PM5350-RC tca 761
Contextual Info: PM5350 S/UNI-ULTRA DATA SHEET PMC-960924 ISSUE 5 SATURN USER NETWORK INTERFACE PM5350 S/UNI- R 155-ULTRA S/UNI-155-ULTRA SATURN USER NETWORK INTERFACE 155.52 & 51.84 MBIT/S DATA SHEET ISSUE 5: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE