TC32D Search Results

GR-1244-CORE

Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1
Contextual Info: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features November 2005 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for

GR-1244-CORE

Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1 TC65D
Contextual Info: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features November 2004 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for

ZL30102

Abstract: GR-1244-CORE ZL30102QDG ZL30102QDG1
Contextual Info: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features • November 2005 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock

Contextual Info: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44

GR-1244-CORE

Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1 T110
Contextual Info: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces Ordering Information *Pb Free Matte Tin

GR-1244-CORE

Abstract: GR-253-CORE ZL30106 ZL30106QDG "network interface cards"
Contextual Info: ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features • • • • • • • • October 2004 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH

Contextual Info: WAN PLL WITH DUAL REFERENCE INPUTS FEATURES • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

Contextual Info: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs

Contextual Info: WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3002A FEATURES • • • • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

32.768mhz ic

Contextual Info: WAN PLL WITH SINGLE REFERENCE CLOCK FEATURES • • • • • • • • • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface

GR-1244-CORE

Abstract: ZL30102 ZL30102QDG ZL30102QDG1
Contextual Info: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features April 2010 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock •

GR-1244-CORE

Abstract: ZL30100 ZL30100QDC ZL30100QD
Contextual Info: ZL30100 T1/E1 System Synchronizer Data Sheet Features June 2004 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbps and 1544 kbps interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces

C155

Abstract: GR-1244-CORE IDT82V3155 TR62411
Contextual Info: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3155 FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application • Supports ITU-T G.813 Option 1 clocks

Contextual Info: WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface

GR-1244-CORE

Abstract: TR62411 PLL 2400 MHZ
Contextual Info: WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface

GR-1244-CORE

Abstract: GR1244-CORE ZL30101 ZL30101QDC ZL30101QDG1
Contextual Info: ZL30101 T1/E1 Stratum 3 System Synchronizer Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 3 • Supports G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces Ordering Information ZL30101QDG1 64 Pin TQFP* Trays, Bake & Drypack

GR-1244-CORE

Abstract: GR-253-CORE MT90866 ZL30105 ZL30105QDG ZL30106 tc84l
Contextual Info: ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 Data Sheet Features June 2004 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock • Supports ITU-T G.813 option 1, G.823 for 2048 kbs

GR-1244-CORE

Abstract: ZL30102 ZL30102QDG
Contextual Info: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features July 2004 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock •

GR-1244-CORE

Abstract: GR1244-CORE IDT82V3011 SSOP56 TR62411
Contextual Info: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44

Contextual Info: WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface

GR-1244-CORE

Abstract: ZL30100 ZL30100QDC ZL30100QDG1
Contextual Info: ZL30100 T1/E1 System Synchronizer Data Sheet Features February 2006 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for

C155

Abstract: GR-1244-CORE IDT82V3155 SSOP56 TR62411
Contextual Info: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3155 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs

GR-1244-CORE

Abstract: GR1244-CORE IDT82V3001A SSOP56 TR62411
Contextual Info: WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface

GR-1244-CORE

Abstract: IDT82V3012 SSOP56 TR62411
Contextual Info: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs