T901 Search Results

transistor t9018

Abstract: 9018 T9018F
Contextual Info: T9018 9018 NPN EPITAXIAL SILICON TRANSISTOR AM/FM IF AMPLIFIER,LOCAL OSCILIATOR OF FM/VHF TUNER * High Current Gain Bandwidth Product fT=1100MHz 1. 1.BASE 2.EMITTER 3.COLLECTOR ABSOLUTE MAXIMUM RATINGS at Ta=25 Rating 2.4 1.3 Unit Vcbo 30 V Collector-Emitter Voltage

Contextual Info: Technische Information / technical information Netz-Thyristor Phase Control Thyristor T901N Key Parameters enndaten VDRM / VRRM 3200V … 3600V ITAVM 940A TC=85°C ITSM vT0 19000A 3570A (TC=55°C) 1,16V rT 0,494mΩ RthJC 17,0K/kW Clamping Force 15 … 24kN

N010-0554-T901

Contextual Info: Part Number: N010-0554-T901

transistor t9018

Abstract: 9018 T9018 T9018F transistor 9018 NPN
Contextual Info: T9018 9018 NPN EPITAXIAL SILICON TRANSISTOR AM/FM IF AMPLIFIER,LOCAL OSCILIATOR OF FM/VHF TUNER * High Current Gain Bandwidth Product fT=1100MHz 1. 1.BASE 2.EMITTER 3.COLLECTOR ABSOLUTE MAXIMUM RATINGS at Ta=25 Rating 2.4 1.3 Unit Vcbo 30 V Collector-Emitter Voltage

KA5Q1265RF

Abstract: BCK-80-F02G-72G C949 AC400V P25SK062 ka5q1265 T29S T25SK076
Contextual Info: P25SK062, T25SK068, T25SK068V, T25SK076. T25SK120, P25SK07K P25SK15K T29SK068. T29SK068V, T29SK076, T29SK178. P29SK061, P29SK067. P29SK077, P29SK15K P29SK151V, P29SK282. T34SK068, T34SK073, T34SK173^0 T901 BCK-80-F026-72G C949 *fa|i _ 2n2/AC400V >♦«5 +5/0

AL 901A

Contextual Info: DA TA S H E E T MARCH 1998 Revision 1.2 T901A/907A Universal Ethernet Transceiver G eneral Description Features The LX T901A and LX T 907A Universal Ethernet Transceivers are new-generation T901 and LXT907 replacements with improved noise immunity and output

907a

Abstract: ATIC 111
Contextual Info: T901A/907A Universal Ethernet Transceiver 19enera! Des on T he L X T 901A and L X T907A U niversal E thernet T rans­ ceivers are new -generation LX T901 and LX T907 replace­ m ents w ith im proved noise im m unity and output filtering. T he feature set of the LX T901A /907A has been stream ­

A63A

Abstract: 74LSOO
Contextual Info: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS642 Hitachi Scans-001
Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The

74LSOO

Contextual Info: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -

74LSOO

Abstract: CI 2210 HD74LSoop
Contextual Info: •T rip le 3-input Positive NOR Gates • C IR C U IT S C H E M A T IC ^ B P IN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 2 0 - +75°C ) Item S ym bol T e s t C o n d itio n s min typ* m ax V lH 2 .0 - - V lL - - 0 .8 U n it Input v o lta g e V

74LSOO

Abstract: 1S2074
Contextual Info: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

Contextual Info: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p

Contextual Info: •D u a l 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item Input voltage O utput voltage Symbol VlH VlL VOH V>L I ih It L ¡1 Input c u rren t S h o rt-c irc u it output c u rren t Supply c u rren t Input clam p voltage

74LSOO

Abstract: HD74LS374 HD74LSoop
Contextual Info: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third

1S2074

Abstract: 74LSOO HD74LS75 Hitachi Scans-001
Contextual Info: •Q uad ru ple Bistable Latches The H D 74LS75 is ideally suited for use as temporary storage for binary information between processing units and input/ • P IN ARRANGEMENT output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is

HD74LS154

Abstract: 74LSOO ir 2210 ic LS2074
Contextual Info: •4-line-to-16-line Decoders/Demultiplexers This decoder utilizes T T L circuitry to decode four binarycoded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The demul­ tiplexing function is performed by using the 4 input lines to

HD74LSoop

Abstract: 74LSOO 400M HD74LS54 Hitachi Scans-001
Contextual Info: •4 -w id e 2-input, 3-input AND-OR-INVERT Gates • C IR C U IT SCHEM ATIC B P IN ARRANGEMENT N ote The schem atic w ith in the dashed line is included the half inp ut term inals o f H D 7 4 L S 5 4 . ■ELECTRICAL CHARACTERISTICS T a = - 20- + 75°C )

74LSOOP

Abstract: 74LSOO
Contextual Info: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions

DP 804 C

Abstract: JV3 diode 74LSOO HD74LS221
Contextual Info: HD74LS221 »Dual Monostable Multivibrators This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the tran­