T18H Search Results

DP83932

Abstract: EISA9032 lh 9032 intel 82596 fci dh 22 T35 12H ix031 LA23-LA13 9010 plx LHi 954
Contextual Info: EISA 9032 T •CHNOLOBV^ EISA Bus Master Interface Chip Intel 82596 Mode APRIL 1993 Patent Pending_ Features_ General Description_ • EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

kjd1

Abstract: t17c marking T18C UT63M125 application notes 1553B F801 UT1553B T16B 3F6 smd smd 3F9
Contextual Info: UT1553B RTR Remote Terminal with RAM FEATURES ❐ Complete MIL-STD-1553B remote terminal interface ❐ 1K x 16 of on-chip static RAM for message data, completely accessible to host ❐ Self-test capability, including continuous loop-back ❐ ❐ ❐ ❐ MCSA 4:0

4279g

Abstract: G52E111 G74B111 ET-46 microtran t5115 IFS-0505 TTC05 TTC 103 2PC 502 m 8044
Contextual Info: ~tamura Product Number Index MICROTRAIM, Part No. Page Part No. Page 1 0A 006 20 3FD -348 18 Part No. 3FS -2120 Page 18 630A4201 33 A K S 25-12 39 DCM 4-PC 10A 007 20 3FD -356 18 3FS -216 18 630 A 4 3 0 4 33 A K S 25-15 39 DCM 5-PC 6 1 0A 008 20 3FD -410 18

T13G

Abstract: T18E t12j A6211 RTS-34 t18f 63M125 t17j UT176 RTS-28
Contextual Info: UTI760A RTS Remote Terminal for Stores FEATURES ❐ Complete MIL-STD-1760A Notice I through III ❐ ❐ ❐ ❐ ❐ ❐ ❐ remote terminal interface 1K x 16 of on-chip static RAM for message data, completely accessible to host Self-test capability, including continuous loop-back

t20s

Abstract: SQFP208 MB86930 MB86936A
Contextual Info: MB86936 930 SERIES 32–BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • JTAG test interface FEATURES • Emulator support hardware • 50 MHz version with clock doubling • SPARC high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754

MB86901

Abstract: MB89251 Fujitsu MB86900 mb86900 MB86902 instruction set Sun SPARC T8 MB86931-20ZF-G
Contextual Info: MB86931 930 Series 32–BIT RISC EMBEDDED PROCESSOR/ INTERRUPT CONTROLLER/TIMER/USART MAY 24, 1994 FEATURES • 40 MHz 25ns/cycle operating frequency • SPARC high performance RISC processor – 2 Kbytes 2–way set associative instruction and data caches.

MB86930

Abstract: QFP-208 fujitsu MB86932-20ZF-G MB86932-40ZF-G MB86932
Contextual Info: MB86932 930 Series 32–BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • • • • • • • • • • • • • • • • • • • • • • • 40 MHz 25ns/cycle operating frequency SPARCR high performance RISC architecture 8 Kbytes 2-way set associative instruction cache

RTS34

Abstract: RTS20 kjd1 t17c SMD MARKING CODE k11 F801 UTI760A MIL-STD-1760A smd 3F9 marking code T16A
Contextual Info: UTI760A RTS Remote Terminal for Stores FEATURES ❐ Complete MIL-STD-1760A Notice I through III ❐ ❐ ❐ ❐ ❐ ❐ ❐ remote terminal interface 1K x 16 of on-chip static RAM for message data, completely accessible to host Self-test capability, including continuous loop-back

MB86901

Abstract: mb86900 Fujitsu MB86900 MB86902 mb86930-40 MB86930-20PFV-G MB86930-40CR-G ASI1 MARKING MB86930 MB86930-30ZF-G
Contextual Info: MB86930 930 Series 32-BIT RISC EMBEDDED PROCESSOR May 25, 1994 Included to maximize the performance of the system with minimum glue logic, are chip select outputs, programmable wait-state generation and built-in support for a high performance connection to page-mode DRAM. See

MB86933H

Abstract: MB86930 MB86931 instruction set Sun SPARC T8 ADR27
Contextual Info: MB86933H 930 Series 32–BIT RISC EMBEDDED PROCESSOR November 1996 ADVANCE INFORMATION FEATURES • 25 MHz 40ns/cycle operating frequency • SPARC V8 high–performance RISC architecture • 1 KByte, direct mapped instruction cache • Flexible locking mechanism for instruction cache

1553B

Abstract: F801 UT1553B 63M125 1553b rti t17c
Contextual Info: UT1553B RTR Remote Terminal with RAM FEATURES ❐ Complete MIL-STD-1553B remote terminal interface ❐ 1K x 16 of on-chip static RAM for message data, completely accessible to host ❐ Self-test capability, including continuous loop-back ❐ ❐ ❐ ❐ MCSA 4:0

mil-std-1760a

Abstract: T18H F801 UTI760A HEX300 MIL-STD-1553B t15e RTS-14 63M125 T16G
Contextual Info: UTI760A RTS Remote Terminal for Stores FEATURES ❐ Complete MIL-STD-1760A Notice I through III ❐ ❐ ❐ ❐ ❐ ❐ ❐ remote terminal interface 1K x 16 of on-chip static RAM for message data, completely accessible to host Self-test capability, including continuous loop-back

MB86930

Abstract: ADR27
Contextual Info: MB86935 930 SERIES 32–BIT RISC EMBEDDED PROCESSOR November 1996 ADVANCE INFORMATION • Parity generation and checking FEATURES • Programmable address decoder and wait-state generator • 66MHz, 80MHz and 100 MHz versions each with clock doubling capability

Contextual Info: 24 993 EISA 9032 r . c^TTSTS-rrr EISA Bus Master Interface Chip Intel 82596 Mode MARCH 1993 Patent Pending_ Features_ General Description_ • EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

OJP 201

Abstract: T45 12H
Contextual Info: EISA 9032 T•CHNOLOBV^ EISA Bus Master Interface Chip Intel 82596 Mode APRIL 1993 Patent Pending_ Features_ General Description_ • EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

dw2 18- 2 5t

Abstract: ic 40113 B648 K66-1 T13G
Contextual Info: UT1760A RTS Remote Terminal for Stores F ea tures I n t r o d u c t io n □ Complete MIL-STD-1760A Notice I through III remote terminal interface The UT1760A RTS is a monolithic CMOS VLSI solution to the requirements of the dual-redundant MIL-STD-1553B interface as specified by

k717

Abstract: t18f T18E K66-1
Contextual Info: Military-Standard Products UT1553B RTR Remote Terminal with RAM Preliminary Data Sheet UNITED TECHNOLOGIES MICROELECTRONICS CENTER May 1989 FEATURES INTRODUCTION □ C om plete M IL-STD-1553B □ IK x 16 of on-chip static RAM for message data, completely accessible to host

TG16C554

Abstract: TG16C550 TG16C550CJ TG16C554CQ tg16c554dcq plcc trasmitter TG16C554CJ 6855I centronics 36 specification UARTs 16C550
Contextual Info: TG16C554 Twist Quad UART with 16-byte FIFO FEATURES GENERAL DESCRIPTION IBM PC/AT and PS/2 compatible Quad UART 16-byte transmit-receive FIFO Selectable receive trigger levels Programmable baud rate generator Modem control signals 3.3V or 5V Operation