SYNOPSYS DC ULTRA Search Results

Contextual Info: Oki Semiconductor MSM13Q/14Q 0.35 |im Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 Jim ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q0000/14Q0000 series devices referred to as "M SM 13Q /14Q " are implemented with the

programming manual EPLD

Abstract: 8 BIT ALU design with vhdl code using structural xilinx epld 16 bit carry lookahead subtractor vhdl ABEL-HDL Reference Manual EPLD cb8cle programmer EPLD XC7000 XC7336
Contextual Info: Getting Started with Xilinx EPLDs Designing with EPLDs Compiling Your Design X2845 Fitting Your Design Xilinx Synopsys Interface EPLD User Guide Simulating Your Design EPLD Architecture Library Component Specifications Attributes Xilinx Synopsys Interface EPLD User Guide — December, 1994 0401289 01

MSM13Q

Abstract: msm 32X32
Contextual Info: Oki Semiconductor MSM13Q/14Q 0.35 |im Sea of Gates Arrays D E SC R IP TIO N O ki's 0.3 5 |_im ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q 0000/14Q 0000 series devices referred to as "M SM 1 3 Q /1 4 Q " are im plem ented with the

verilog code for UART with BIST capability

Abstract: VHDL CODE FOR HDLC controller ARM dual port SRAM compiler DesignWare SPI vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Sun Enterprise 250 static SRAM single-port verilog code for 16 bit risc processor verilog code arm processor
Contextual Info: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

ahb arbiter in mentor

Abstract: 16x16x1.4
Contextual Info: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 0.5 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

144 QFP body size

Abstract: 35x35 bga BGA and QFP Package vhdl code for usart DesignWare SPI 0.18-um CMOS technology characteristics ARM7 verilog code NEC-V850 PZT driver design vhdl coding for analog to digital converter
Contextual Info: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.0 April 6, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

ARM dual port SRAM compiler

Abstract: rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110
Contextual Info: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device

DSPG

Abstract: Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler
Contextual Info: V S MSUNG STD131 ELECTRONICS STD131 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device

synopsys Platform Architect

Abstract: clock tree balancing DesignWare SPI vhdl code for watchdog timer of ATM 0.18-um CMOS technology characteristics vhdl coding for analog to digital converter CML Vterm 27x27
Contextual Info: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.1 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

verilog code voltage regulator

Abstract: verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C
Contextual Info: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.2 May 17, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

datasheet of BGA Staggered pins

Abstract: NEC-V850 VHDL CODE FOR HDLC controller vhdl code for 4 channel dma controller clock tree balancing serdes transceiver 1999 verilog code for i2c vhdl code download for memory in cam vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter
Contextual Info: GS30 0.15-µm CMOS Standard Cell/Gate Array High-Value ASIC ❑ 0.15-µm Leff process 0.18-µm drawn with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O ❑ 4 and 5 levels of metal ❑ 6 million random logic gates plus 6 million

ternary content addressable memory VHDL

Abstract: ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge
Contextual Info: V S MSUNG STDL150 ELECTRONICS STDL150 Standard Cell 0.13um System-On-Chip ASIC March 2003, V2.0 Features Analog cores - Ldrawn = 0.13um 1.5/2.5/3.3V Device 1.5/2.5/3.3V - Up to 45.8 million gates Interface - Power dissipation: 13nW/MHz@1.5V, 2SL, ND2 5.0V

MSM13Q

Abstract: L9013Q13Q
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MSM13/14Q 0.35 µm Sea of Gates Arrays August 2002 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

verilog code for 32 bit risc processor

Abstract: vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design
Contextual Info: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 September 23, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

MSM13Q

Abstract: base cell floorplan io uart vhdl
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MSM13Q/14Q000 0.35 µm Sea of Gates Arrays November 1999 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

verilog code for UART with BIST capability

Abstract: vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave
Contextual Info: SR40 0.095-µm High-Speed Copper Standard Cell/Gate Array ASIC Version 1.1 May 17, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

539 b14

Abstract: oki cross MG73Q MG74Q MSM98Q MSM99Q M98Q memory compiler
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MG73/74Q and MSM98Q/99Q 0.35µm Customer Structured Arrays August 2002 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

ms3400

Abstract: "module compiler" APEX20K APEX20KE 8051 keyboard design methodology
Contextual Info: FPGA Express Getting Started Version 3.4, March 2000 Comments? E-mail your comments about Synopsys documentation to doc@synopsys.com Copyright Notice and Proprietary Information Copyright  2000 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary

n117

Abstract: pinout of bel 187 transistor decoder in verilog with waveforms and report EPIC-1 sol 20 Package XILINX x8086 XC2064 XC3090 XC4005 XC5210
Contextual Info: Quick Start Guide for Xilinx Alliance Series 1.4 Introduction Installation Alliance Series Design Implementation Tools Tutorial How This Release Works Cadence Concept and Verilog Interface Notes Alliance FPGA Express Interface Notes Mentor Graphics Interface

10R0000

Contextual Info: Prelim inary O K I Semiconductor M SM 1 0 R 0 0 0 0 _ 0.5nm Sea of Gates Family for Very High-Performance, 3.3 Volt Applications DESCRIPTION The OKI MSMIOROOOO Sea of Gates SOG family is an ultra high-speed, low-power and very high density semicustom product based upon OKI's 0.5]^m drawn (0.4jrm effective) CMOS technology,

CG51754

Abstract: fujitsu asic CE51654 CG51114 CG51284 CG51364 CG51484 CG51214 CG51654 CG-51
Contextual Info: cP FUJI' Novem ber 1995 Edition 1.5 DATA SHEET = - ' CG51/CE51 SERIES 3V, 0.50 MICRON HIGH PERFORMANCE/LOW POWER CMOS GATE ARRAYS DESCRIPTION The Fujitsu CG51/CE51 is a series of ultra high performance CMOS gate arrays. The CG51 is a high density Sea-of-Gates

tsmc 130nm metal process

Abstract: teradyne tiger aeroflex sram edac charactristics of cmos logic gates CCGA 472 leon3 teradyne flex tester CCGA 472 drawing 130NM cmos process parameters tsmc cmos
Contextual Info: Semicustom Products UT130nHBD Hardened-by-Design HBD Standard Cell Advanced Data Sheet August 2010 www.aeroflex.com/RadHardASIC FEATURES PRODUCT DESCRIPTION ‰ Up to 15,000,000 usable equivalent gates using standard cell architecture The high-performance UT130n HBD Hardened-by-Design

NEC V30MX

Abstract: 8255a Max mode system in 8086 microprocessor v 12719 40673 71055 Rambus ASIC Cell 40673 cmos marking code C76 verilog code for 8254 timer IC Ensemble
Contextual Info: CB-C8 3-VOLT, 0.5-MICRON CELL-BASED CMOS ASIC NEC Electronics Inc. July 1994 Description Figure 1. Typical CB-C8 Series Cell-Based ASIC NEC’s 3-volt CB-C8 cell-based ASIC series are ultra-high performance sub-micron CMOS products built within the OpenCAD Design SystemTM of NEC. The family allows

atmel h 208

Abstract: atmel1 atmel 216
Contextual Info: ATLV Features • Specifically Designed for Battery Powered Applications 1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts • Static Current Drain of <75 nA at 1.0 Volts • 200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts • 1.0 n Drawn Gate Length CM OS Gate Arrays