SYNC12 Search Results

Z80180

Abstract: Zilog z180 Z8018233FSC Z80180 technical manual Z80182 ESCC technical manual z182 Z180 Z180 mpu Zilog 85230 z180 controller
Contextual Info: Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y P RELIMINARY P RODUCT S PECIFICATION Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL CONTROLLER ZIP FEATURES • Z8S180 MPU - Code Compatible with Zilog Z80 /Z180™ CPU - Extended Instructions

Nx62

Abstract: DS3100 DS3104GN DS3104-SE GR-1244-CORE GR-253-CORE GR-499-CORE
Contextual Info: Rev: 072407 DS3104-SE Line Card Timing IC with Synchronous Ethernet Support General Description The DS3104-SE is a low-cost, feature-rich timing IC for line cards with synchronous Gigabit Ethernet GbE , 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports.

DS3100

Abstract: DS3105 DS3105LN GR-1244-CORE GR-253-CORE LQFP64 MCR10 ACS8525 MCR10 ROHS D1801
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing

zct02

Abstract: SZ1 AMI
Contextual Info: P r e l im in a r y P r o d u c t S p e c if ic a t io n V % Z80185/Z80195 S m a r t P e r ip h e r a l C o n t r o l l e r s FEATURES • 0°C to +70°C Temperature Range ■ Enhanced Z8S180 MPU ■ Four Z80 CTC Channels 100-Pin QFP Package ■ One Channel ESCC” Controller

Z08030, Z08530

Abstract: Z8523010VSC Z85230 Z8523010VEC Z8523016VEC ESCC technical manual IN SDLC PROTOCOL Z08030 Z8523020PSC M043
Contextual Info: Pr o d u c t S p e c if ic a t io n < £ 2 iL Œ Z85230 ESCC Enhanced S erial Com m unication Controller FEATURES • Deeper Data FIFOs - 4-Byte Transmit FIFO - 8-Byte Receive FIFO ■ Programmable FIFO Interrupt Levels Provide Flexible Interrupt Response

Contextual Info: Rev: 120707 DS3105 Line Card Timing IC Features General Description The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically, the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs

nx10 alarm system

Abstract: nx10 alarm
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3102 is a highly integrated central timing and

Contextual Info: Rev: 070308 DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of

Contextual Info: Rev: 012108 DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support Features General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of

Z8030ACS

Abstract: Z8030APS Z8030A IN SDLC PROTOCOL USING SCC WITH Z8000 IN SDLC PROTOCOL CRC-16 Z8000 Z8030 z-scc Z8030 PS
Contextual Info: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog A pril 1985 • Two in dependent, 0 to 1.5M bit/second, fullduplex channels, eac h with a separate crystal oscillator, b a u d rate generator, a n d Digital Phase-L ocked Loop for clock recovery.

PS011701-0701

Contextual Info: Z80C30/Z85C30 CMOS SCC Serial Communications Controller Product Specification PS011701-0701 ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether

Contextual Info: Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y P RELIMINARY P RODUCT S PECIFICATION Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL CONTROLLER ZIP FEATURES • Z8S180 MPU - Code Compatible with Zilog Z80 /Z180™ CPU - Extended Instructions

VL8530

Abstract: IN SDLC PROTOCOL NMOS8530 VL85C35-04CC VL85C35-04PC VL85C35-04QC VL85C35-06CC VL85C35-06PC VL85C35-06QC til 312
Contextual Info: VL85C35 ? o' ENHANCED SERIAL COMMUNICATIONS CONTROLLER ESCC FEATURES DESCRIPTION • The VLB5C35 CMOS Enhanced Serial Communications Controller (ESCC) is a dual-channel, multi-protocol data communications peripheral designed for use with non-multiplexed buses.

thomson RT 463 Schematic

Abstract: Z8530 F 0513A fli5 WR1 marking code IN SDLC PROTOCOL PLCC44 RR15 WR10 ZS330
Contextual Info: SGS-THOMSON Z8530 SERIAL COMMUNICATIONS CONTROLLER Thank you for your interest in the SCC, one of the most versatile and most popular Serial Data Com ­ munications ICs. This document is intended to pro­ vide answers to all technical questions about the Z8530 Serial Communications Controller. Please

Contextual Info: Pr o d u c t S p e c if ic a t io n < £ 3 L0 E Z85230 E S C C E n h a n c e d S e r ia l C o m m u n ic a t io n C o n t r o l l e r FEATURES • Deeper Data FIFOs - 4-Byte Transm it FIFO - 8-Byte Receive FIFO ■ Program m able FIFO Interrupt Levels Provide Flexible

TCXO 30.72MHz

Abstract: 30.72MHZ oscillator 0.02PPM 3.3 TCXO 24.576 ACS8525 DS3100 DS3105 DS3105LN GR-1244-CORE GR-253-CORE MCR10
Contextual Info: 19-4628; Rev 3; 5/09 DS3105 Line Card Timing IC Features General Description The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically, the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs

ACS8522

Abstract: 10mhz OCXO Digital Alarm Clock by ttl DS3102 DS3102GN GR-1244 GR-1244-CORE GR-253 GR-253-CORE
Contextual Info: 19-4617; Rev 5; 8/10 DS3102 Stratum 2/3E/3 Timing Card IC with Synchronous Ethernet Support General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of

transistor marking WR5 72

Abstract: txc xtal sdlc ibm signals z8030 DDR14
Contextual Info: < 2 > 2 iL G E Pr o d u c t S p é c if ic a t io n Z16C35/Z85C35 CMOS ISC C INTEGRATED SERIAL C o m m u n ic a t io n s C o n t r o l l e r FEATURES • Two general-purpose SCC channels, four DMA channel; and a Universal Bus Interface Unit. ■ Software compatible to the Zilog CMOS SCC

Z8523016VEC

Abstract: Z8523016vsc Z8523016PEC Z8523008VSC z8523010vsc Z8523020PSC z85230 z08030
Contextual Info: i £ S L C E P r o d u c t S p e c if ic a t io n Z85230 ESCC ENHANCED S E R IA L C o m m u n ic a t io n C o n t r o l l e r FEATURES • Deeper Data FIFOs - 4-Byte Transmit FIFO - 8-Byte Receive FIFO ■ Programmable FIFO Interrupt Levels Provide Flexible

marking wr6

Contextual Info: U s e r 's M a n u a l ^ S iL G E C hapter 5 R e g is t e r D e s c r ip t io n s 5.1 INTRODUCTION This section describes the function of the various bits in the registers of the device. Throughout this section the follow­ ing conventions will be used: Control bits may be written and read by the CPU and will

Contextual Info: PRELIMINARY PRODUCT SPECIFICATION < £ Z iIi3 G Z80181 Z181 SAC S mart A c c e s s C ontroller FEATURES • Z80180CompatibleMPUCore with 1 channel of Z85C30 SCC, Z80 CTC, two 8-bit general purpose parallel ports, and two chip select signals. ■ High speed operation 10/12.5 MHz

Contextual Info: P ro du c t S pecificat io n < £ Z iIß ö Z80C30/Z85C30 CMOS Z-BUS SCC S e r ia l C o m m u n ic a t io n C o n t r o l l e r FEATURES • Low power CMOS ■ Pin compatible fo NMOS versions ■ Two independent, 0 to 4.1 Mbit/second, full-duplex channels, each with a separate crystal oscillator, baud

Contextual Info: »2 JLC E PRELIMINARY PRODUCT SPECIFICATION Z 80185/ Z 80 1 95 SMART PERIPHERAL CONTROLLERS FEATURES • Z80185: 32 Kbytes ROM Z80195: ROMIess ■ Enhanced Z8S180 MPU - Code Compatible with Zilog's Z80 /Z180w CPUs - Extended Instructions - Two Enhanced DMA Channels

SM TX 433

Abstract: SYNC12 CRC16
Contextual Info: < 2 > 2 iL 0 E PRELIMINARY PRODUCT SPECIFICATION Z80181 ZIO C o n t r o l le r ZILOG I/O C o n t r o lle r FEATURES • Z 8 0 180 C om patible MPU Core with 1 channel of Z85C30 SCC, Z80 CTC, two 8-bit general purpose parallel ports, and two chip select signals.