SY10H603JCTR Search Results

Contextual Info: * 9-BIT LATCHED ECL-TO -TTL SYNERGY SY10H603 SY100H603 S E M IC O N D U C T O R FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply

Contextual Info: SY10H603 SY100H603 FINAL 9-BIT LATCHED ECL-TO-TTL DESCRIPTION FEATURES Q8 GND Q7 BLOCK DIAGRAM Q6 PIN CONFIGURATION GND VCCT 25 24 23 22 21 20 19 Q4 26 18 Q3 27 17 D8 D7 VCCT 28 16 VCCE Q2 1 15 GND Q1 Q0 2 D6 D5 OEECL D0 D Q Q0 EN D1 D Q Q1 EN D2 D Q TOP VIEW

SY100H603

Abstract: SY100H603JC SY10H603 SY10H603JC SY10H603JCTR
Contextual Info: SYNERGY SY10H603 SY100H603 9-BIT LATCHED ECL-TO-TTL SEMICONDUCTOR SYNERGY SY10H603 SY100H603 SEMICONDUCTOR DESCRIPTION FEATURES • 9-bit ideal for byte-parity applications ■ 3-state TTL outputs ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize

Contextual Info: 9 - BI T L A T C H F H SYNERGY :w I 0 H 603 ECL-TQ-TTv ;ii0H603 S E M IC O N D U C T O R FE A T U R E S D E S C R IP TIO N 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize

SY100H603

Abstract: SY10H603 ICCZ80
Contextual Info: * 9-BIT LATCHED ECL-TO-TTL SYNERGY S E M IC O N D U C T O R FEA TU R E S t S Y10H 603 S Y100H 603 D ES C R IPTIO N 9-bit ideal for byte-parity applications 3-state TTL outputs The S Y 10/100H 603 are 9-bit, dual supply ECL-to-TTL translators. Devices in the Synergy 9-bit translator series

Contextual Info: * 9-BIT LATCHED ECL-TO-TTL SYNERGY SY10H603 SY100H603 SEMICONDUCTOR DESCRIPTION FEATURES • 9-bit ideal lor byte-parity applications ■ 3-state TTL outputs ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise

SY100H603

Abstract: SY10H603 SY10H603JC
Contextual Info: • ■ ■ ■ ■ ■ 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply 6.0ns max. delay into 50pF, 12ns into 200pF all outputs switching

SY100H603

Abstract: SY100H603JC SY10H603 SY10H603JC SY10H603JCTR
Contextual Info: 9-BIT LATCHED ECL-TO-TTL DESCRIPTION FEATURES Q8 GND Q7 BLOCK DIAGRAM Q6 PIN CONFIGURATION GND VCCT 25 24 23 22 21 20 19 Q4 26 18 Q3 27 17 D8 D7 VCCT 28 16 VCCE Q2 1 15 GND Q1 Q0 2 D6 D5 OEECL D0 D Q Q0 EN D1 D Q Q1 EN D2 D Q TOP VIEW PLCC 14 3 13 4 12 Q2

Contextual Info: >0 » SYNERGY 9-BIT LATCHED ECL-TO-TTL SY10H603 SY100H603 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply

Contextual Info: >0 » SYNERGY 9-BIT LATCHED ECL-TO-TTL SY10H603 SY100H603 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply