SY100S838ZCTR Search Results

100S838L

Contextual Info: V • SYNERGY 2n s o r ' : a 4 ei : ;.o c k î î e n f r a m ^ Z M c v H a w .„ if \8 S E M IC O N D U C 1O R F EA TU R E S D ES C R IPTIO N • 3.3V and 5V pow er supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ M aster Reset for synchronization

Contextual Info: >0 » SYNERGY -1 ,^ /3 OR (*2, *4/6) c l o c k g e n e r a tio n chip SEMICONDUCTOR • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KÌ2 input pull-down resistors

113006

Abstract: SY100S838ZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZCTR SY100S838ZI SY100S838LZGTR
Contextual Info: ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP Micrel, Inc. Precision Edge Precision SY100S838 Edge® SY100S838L SY100S838 SY100S838L FEATURES • ■ ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable

SY100S838

Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR 100S838L
Contextual Info: SYNERGY ClockWorks SY100S838 ClockWorks™ SY100S838L ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP SEMICONDUCTOR SYNERGY SY100S838 SY100S838L SEMICONDUCTOR FEATURES DESCRIPTION • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable

Contextual Info: +1, +2/3 OR (+2, * 4 /6 ) c l o c k g e n e r a t i o n c h ip SYNERG Y C'QS 0 S 8 3 8 s y io o s s 3 8 l SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization

SY100S838

Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR
Contextual Info: ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are

Contextual Info: M , +2/3 OR +2, +4/6) CLO CK GENERATIO N CHIP SYNERGY S E M IC O N D U C T O R FEATURES • ■ ■ ■ ■ ■ C'°S Y^0S838 Sy 10Qs83bl S Y 100S 838L DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization

SY100S838

Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR
Contextual Info: ClockWorks SY100S838 SY100S838L FINAL ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are

Contextual Info: >0 » SYNERGY -1, ^2/3 OR (-2, ^1/6) c l o c k g e n e r a tio n chip SEMICONDUCTOR • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KÌ2 input pull-down resistors