STO8B Search Results

TDA 2025

Abstract: Z80 CPU PHYSICAL DIMENSIONS LCC tda 2015 Z84C0006CMB TDA 2025 chip z84c0006 cpu Z80 CPU DIMENSIONS centrifuge machine for acceleration 84C0006 zilog z80 dynamic ram Application
Contextual Info: ZILOG 9984043 ZILO G INC 03 DËJ 4 0 4 3 03E IN C IL ITA R Y 000044 2 5 | ~ 08442 ¿S, roduct S p ecification l : April 1988 Z84C00 CMOS Z80 CPU Central Processing Unit T - H q - n - o i FEATURES • The CMOS Z80 combines the high performance of the

ZL50011QCG1

Abstract: GR-1244-CORE MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack

ZL50010

Abstract: TFR1M GR-1244-CORE MS-026
Contextual Info: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15

GR-1244-CORE

Abstract: MS-026 ZL50011 11CH marking
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

BC1211

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

GR-1244-CORE

Abstract: MS-026 ZL50010
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

ZL50010QCG1

Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

MS-026

Abstract: ZL50012
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

GR-1244-CORE

Abstract: MS-026 ZL50010 TFPW0
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

MS-026

Abstract: ZL50012 philips e3 STO11 ci 116h 4094m
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

FOX 20.000 MHZ

Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS

ZL50012QCG1

Abstract: MS-026 ZL50012 STO10
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • April 2006 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • September 2011 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information ZL50011/GDC 144 Ball LBGA Trays ZL50011QCG1 160 Pin LQFP* Trays, Bake & Drypack

Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

MS-026

Abstract: ZL50012 TFPW0 sto8b
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

DS5722

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

filter FP1P

Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay