STM-16 TIMING SOURCE Search Results

DIP10

Abstract: DIP12 GD16523 GD16523-100BA
Contextual Info: 2.5 Gbit/s 16:1 Multiplexer GD16523 an Intel company Preliminary General Information Features The GD16523 is a multirate STM 1/4/16 plus 1.25 Gbit/s bit-rates 16:1 re-timing multiplexer with jitter clean-up capability. The VCXO reference clock input is differential and the frequency is selectable

DIP10

Abstract: DIP12 GD16523
Contextual Info: an Intel company 2.5 Gbit/s 16:1 Multiplexer GD16523 General Information Features The GD16523 is a multirate STM 1/4/16 plus 1.25 Gbit/s bit-rates 16:1 re-timing multiplexer with jitter clean-up capability. The VCXO reference clock input is differential and the frequency is selectable

Contextual Info: VSC8146 Datasheet FEATURES ● STS-48/STM-16, FEC ● On-board FIFO ● Wide-ranging PLLs ● Equipment and Facility Loopback modes ● Exceeds Telcordia SONET jitter specifications ● Rx/Tx internal Loop Timing mode ● High-speed data I/O and clock outputs

me520B

Abstract: 04216 RCO12 TXC-04216AIBG TXC-06103
Contextual Info: E1Mx16 Device E1 Mapper 16-Channel TXC-04216 DATA SHEET FEATURES DESCRIPTION • Add/drop sixteen 2.048 Mbit/s signals from an STM-1 VC-4/AU-3, STS-3, or an STS-1 • Independent add and drop bus timing modes • Selectable HDB3 positive/negative rail or NRZ E1

Contextual Info: E1Mx16 Device E1 Mapper 16-Channel TXC-04216 TECHNICAL OVERVIEW PRODUCT PREVIEW FEATURES DESCRIPTION • Add/drop sixteen 2.048 Mbit/s signals from an STM-1 VC-4/AU-3, STS-3, or an STS-1 • Independent add and drop bus timing modes • Selectable HDB3 positive/negative rail or NRZ E1

t25f1

Abstract: TPI44 TNI12
Contextual Info: E1Mx16 Device E1 Mapper 16-Channel TXC-04216 DESCRIPTION • Add/drop sixteen 2.048 Mbit/s signals from an STM-1 VC-4/AU-3, STS-3, or an STS-1 • Independent add and drop bus timing modes • Selectable HDB3 positive/negative rail or NRZ E1 interface. Performance counter provided for illegal

04216

Abstract: transwitch JESD22-A112-A TXC-06103 272a1
Contextual Info: E1Mx16 Device E1 Mapper 16-Channel TXC-04216 DESCRIPTION • Add/drop sixteen 2.048 Mbit/s signals from an STM-1 VC-4/AU-3, STS-3, or an STS-1 • Independent add and drop bus timing modes • Selectable HDB3 positive/negative rail or NRZ E1 interface. Performance counter provided for illegal

Contextual Info: NE555 SA555 - SE555 GENERAL PURPOSE SINGLE BIPOLAR TIMERS . LOW TURN OFF TIME . MAXIMUM OPERATING FREQUENCY GREATER THAN 500kHz . TIMING FROM MICROSECONDS TO HOURS . OPERATES IN BOTH ASTABLE AND MONOSTABLE MODES . HIGH OUTPUT CURRENT CAN SOURCE OR SINK200mA

MIPI system trace protocol

Abstract: SBZP ARM Debug Interface v5 architecture specification Coresight ihi 0029 ARM IHI 0031 ARM IHI 0029 ATID A-100 A-102
Contextual Info: System Trace Macrocell Programmers’ Model Architecture Specification Version 1.0 Copyright 2010 ARM. All rights reserved. ARM IHI 0054A ID090710 System Trace Macrocell Programmers’ Model Architecture Specification Version 1.0 Copyright © 2010 ARM. All rights reserved.

MIPI system trace protocol

Abstract: ATB flush AMBA AXI dma controller designer user guide CoreSight Architecture Specification DMA-330 PR430-PRDC-011726 MIPI system trace coresight state diagram of AMBA AXI protocol v 1.0 AMBA AXI
Contextual Info: CoreSight System Trace Macrocell Revision: r0p0 Technical Reference Manual Copyright 2010 ARM. All rights reserved. ARM DDI 0444A ID090310 CoreSight System Trace Macrocell Technical Reference Manual Copyright © 2010 ARM. All rights reserved. Release Information

STM16

Abstract: G703 PE-65507 SSSB149 SSSB153
Contextual Info: SSSB153 STM16 - STM1 DeMultiplexer SDH Product Range STM16 - STM1 DEMULTIPLEXER The SSSB153 receives STM16 frames in 2 byte parallel form, and sends out selected STM1 frames in bit serial form. Each SSSB153 selects up to four STM1 frames out of the incoming STM16 frame. Up to four SSSB153 devices,

Contextual Info: VITESSE 1 SEMICONDUCTOR CORPORATION Prelim inary Datasheet 2.488 Gb/s ATM/SDH/SONET STM-16/STS-48 Mux/Demux and Section Terminator !C Chipsei VSC8023/VSC8024 Features VSC8024 DEMUX VSC8023 (MUX) • SDH/SONET compliant multiplexing of four by te-wide STM-4/STS-12 data streams into one

RAM 2112 256 word

Abstract: A 69258 0398C 0804B c548 PAR16 spru288 TMS320C5xx transistor BC 945 transistor c548
Contextual Info: TMS320C548/C549 Bootloader and ROM Code Contents Technical Reference Literature Number: SPRU288A October1998 – Revised May 2000 Preface Read This First About This Manual This document describes the operation of the TMS320C548/C549 bootloader and the process used to select the operating mode. The document also provides source code for the bootloader and discusses the other on-chip ROM

S3001-C250

Abstract: water filling station circuit diagram enocean stm 110 H3004-G100 marking STM250
Contextual Info: Radio Magnet Contact STM 250 User Manual V1.4 July 2005 Revision History The following major modifications and improvements have been made to the first version of this document V1.0 : Version Major Changes V1.1 V1.2 • • • • • V1.3 • • • •

TM320C54x

Abstract: pcf8582 TM320C SN54HC125 SN74HC125 TMS320C5000 TMS320C5410 1010B 74HC125 TMS320C54x transmitter
Contextual Info: Application Report SPRA836 - August 2002 Interfacing the TMS320C54x DSP to an I2C Bus Francis Kua Yip Chan Hoe TI Singapore ABSTRACT This application report describes the way to interface the TMS320CX54x digital signal processor DSP with an I2C device. The setup uses the multichannel buffered serial port

Contextual Info: SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS S C B S 6 8 6 -A P R IL 1997 Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access

Contextual Info: • ^302331 □□□3337 SOI ■ SEM IC ONDU^^f^W l^W \m !^ Preliminary Datasheet 2.488 Gb/s atm / s d h / s o n e t s t m - w / s t s -48 Mux/Demux and Section Terminator 1C Chipsei VSC8023/VSC8024 Features VSC8024 DEMUX VSC8023 (MUX) • SDH/SONET compliant multiplexing of four

security system block diagram

Abstract: TMS320C54x SPEECH PROCESSING tlv320aic Architecture of TMS320C54XX block diagram of of TMS320C54X DSK tms320C5402 latest laptop motherboard circuit diagram TMS320C5402 C5402 TLV320AIC10
Contextual Info: Application Report SLAA109 - November 2000 Interfacing the TLV320AIC10/11 Codec to the TMS320C5402 DSP Wendy X. Fang and Perry Miller AAP Data Conversion ABSTRACT This report describes how the analog interface circuit AIC device TLV320AIC10/11, 16-bit, 22-ksps audio codec has been applied in telephony (tone generation and echo cancellation)

security system block diagram

Abstract: tms320vC5402 starter kit board diagram TMS320VC5402 DSK SPRU172B TMS320C54x dsp reference set latest laptop motherboard circuit diagram TMS320C5402 PC MOTHERBOARD skeleton CIRCUIT diagram tms320vC5402 starter kit C5402
Contextual Info: Application Report SLAA109 - November 2000 Interfacing the TLV320AIC10/11 Codec to the TMS320C5402 DSP Wendy X. Fang and Perry Miller AAP Data Conversion ABSTRACT This report describes how the analog interface circuit AIC device TLV320AIC10/11, 16-bit, 22-ksps audio codec has been applied in telephony (tone generation and echo cancellation)

SN54ABT8996

Abstract: SN74ABT8996
Contextual Info: SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS SC BS489B - A U G U S T 1994 - REVISED D ECE M B ER 1996 SN54ABT8996 . . . JT PACKAGE SN74ABT8996 . . . DW OR PW PACKAGE (TOP VIEW ) Members of Texas Instruments Broad

SS3513

Abstract: TCM120 kester 245 solder wire enocean stm 110 RCM120 ss3513 solar cell 1S2463 schematic diagram cm 30- 24 V solar charge controller PTM200 120C
Contextual Info: USER MANUAL V1.26 RF Sensor Transmitter Module STM 11x June 25, 2009 Patent protected: WO98/36395 DE 100 25 561 DE 101 50 128 WO 2004/051591 DE 103 01 678 A1 EnOcean GmbH Kolpingring 18a 82041 Oberhaching Germany Phone +49.89.67 34 689-0 Fax +49.89.67 34 689-50

TMS320C543

Abstract: PEB2186 TMS320C54X addressing modes bpra pin diagram of of TMS320C54X 1S1588 PSB2186 SN74AS869 SN74HC14 block diagram for barrel shifter
Contextual Info: IOM-2 Interfacing on TMS320C54x Literature Number: BPRA074 Texas Instruments Europe February 1998 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

HT66F40

Contextual Info: Using the STM Timer Function in the HT66F40 Using the STM Timer Function in the HT66F40 D/N：HA0249E Introduction The HT66Fx0 series devices include what are known as Timer Modules, which have multiple functions and combine features such as Timer and PWM output generation into a

TMS320C548

Abstract: TMS320C542 block diagram of of TMS320C54X 1000H TMS320 TMS320C57 TI AR7 TI AR7 pin
Contextual Info: The TMS320C54x DSP HPI and PC Parallel Port Interface Application Report 1997 Digital Signal Processing Solutions Printed in U.S.A., March 1997 SPRA151 The TMS320C54x DSP HPI and PC Parallel Port Interface Oh Hong Lye Customer Applications Center TI Singapore