STM-16 ARCHITECTURE Search Results

SDH 209

Abstract: 1xVC4-16c CY7C9538 CYS25G0101DX VC45V
Contextual Info: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as

SFP EVAL BOARD

Abstract: STS-48 XRT91L82 power supply tester schematic diagram EVM-91L82
Contextual Info: EVM-91L82 STS-48/STM-16 SONET/SDH XRT91L82 Evaluation Board User Manual Jul 25, 2006 2.488/2.667 GBPS STS-48/STM-16 SONET/SDH XRT91L82 Transceiver Evaluation Board User Manual 1 EVM-91L82 STS-48/STM-16 SONET/SDH XRT91L82 Evaluation Board User Manual Jul 25, 2006

10UTOPIA

Abstract: CY7C9537B CYS25G0101DX 6AE11
Contextual Info: CONFIDENTIAL CY7C9537B OC-48/STM-16 Framer–POSIC2G Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated — Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] — Complies with Bellcore GR253 rev.1, 1997[3]

D1 3009k

Abstract: 6 pin 2D 1002 ring COUNTER
Contextual Info: IBM3009K2672 IBM SONET/SDH Framer Features • Integrated clock recovery and synthesis for four OC-3c/STM-1 signals or one OC-12/OC-12c/ STM-4/STM-4c signal • OC-12/STM-4 or quad OC-3c/STM-1 framing and performance monitoring • Expansion port for OC-48/STM-16 operation

T1X15

Abstract: CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX
Contextual Info: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997

VSC8115

Abstract: OC-48 AU-4-16c VSC8144 VSC9182 VSC9184 474-pin
Contextual Info: Pointer Processor and Frame Aligner VSC9184 Product Brief TimeStream Product Family Features & Benefits: • Bi-directional STS-48/STM-16, Quad STS-12/STM-4, or Quad STS-3/STM-1 Section and Line Termination Device with Integrated Pointer Processing • Optional STS-3|12/STM-1|4 to

S3047

Abstract: U311D XS-3045
Contextual Info: PRELIMINARY DEVICE SPECIFICATION > 4 M C SO N E T/SD H O C -12 TO OC-48 MUX/DEIWUX FEATURES • Complies with ANSI, Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data

Contextual Info: DEVICE SPECIFICATION SONET/SDH OC-12 TO OC-48 MUX/DEMUX SONET/SDH OC-12 TO OC-48 MUX/DEMUX S3045 S3045 APPLICATIONS FEATURES • Complies with Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data

Contextual Info: DEVICE SPECIFICATION > 4M C SONET/SDH OC-12 TO OC-48 MUX/DEMUX FEATURES • Complies with ANSI, Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data • 8-bit LVTTL data path with parity for each

sd 4841 p

Contextual Info: DEVICE SPECIFICATION SONET/SDH OC-12 TO OC-48 MUX/DEMUX SONET/SDH OC-12 TO OC-48 MUX/DEMUX S3045 S3045 APPLICATIONS FEATURES • Complies with Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data

BCM8228

Abstract: OC48 STM-16 STS-48
Contextual Info: BCM8228 VARIRATE MULTIRATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PERFORMANCE MONITORING SUMMARY OF BENEFITS FEATURES • Highly integrated rate-adaptation device that maps a single STS-3/ STM-1 or a single STS-12/STM-4 stream into STS-48/STM-16 frames

GR-253

Abstract: TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7 ast0
Contextual Info: Advance Data Sheet February 2000 TRCV012G5 2.5 Gbits/s and TRCV012G7 2.7 Gbits/s Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features • TRCV012G5 supports OC-48/STM-16 data rate ■ TRCV012G7 supports: — OC-48/STM-16 data rate — RS 255, 239 forward error correction (FEC)

stm 16 muxponder

Abstract: TXC-06742 stm 4 muxponder telecom bus STM-16 intel Architecture stm 16 mapper STM-16 STM-16 Architecture ETHERMAP-3 PacketTrunk
Contextual Info: TXC-06742 EtherPHAST -48 Plus Highly Integrated Ethernet + SAN Framer/ Mapper for OC-48/STM-16 SONET/SDH Transport KEY BENEFITS Your Intelligent Choice for OC-48/STM-16 Transport of GE, SAN, and FE Streams Flexible Ethernet and SAN terminal interface

si5100h

Contextual Info: Si5100 SiPHY OC-48/STM-16 SONET/SDH T RANSCEIVER Features Complete, low-power, high-speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX  Data rates supported:  SONET-compliant loop timed OC-48/STM-16 through 2.7 Gbps

comcode

Abstract: GR-253 TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7
Contextual Info: Preliminary Data Sheet August 2000 TTRN012G5 2.5 Gbits/s and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer Features • TTRN012G5 supports OC-48/STM-16 data rate ■ TTRN012G7 supports: — OC-48/STM-16 data rate — RS (255, 239) forward error correction (FEC)

GR-253-CORE

Abstract: OC48 Si5018 Si5018-BM STM-16
Contextual Info: Si5018 SiPHY OC-48/STM-16 C LOCK AND D ATA R ECOVERY IC W ITH FEC Features Complete high-speed, low-power, CDR solution includes the following: ! Supports OC-48 /STM-16 & FEC ! Low power—270 mW typ OC-48 ! ! Small footprint: 4x4 mm ! DSPLL™ Eliminates external !

lvds MUX/DEMUX

Abstract: BCM8228 STM-16
Contextual Info: BCM8228 VARIRATE MULTI-RATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PM SUMMARY OF BENEFITS FEATURES • Highly integrated rate adaptation device that maps a single STS-3/ STM-1 or a single STS-12/STM-4 stream into STS-48/STM-16 frames • Channel Add/Channel Extract functionality for mapping and

Si5100

Contextual Info: Si5100 SiPHY OC-48/STM-16 SONET/SDH T R A N S C E I V E R Features Complete, low-power, high-speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX Data rates supported: SONET-compliant loop timed OC-48/STM-16 through 2.7 Gbps

GR-253-CORE

Abstract: Si5320 Si5364 Si5540
Contextual Info: Si5540 P R E L I M I N A R Y D A TA S H E E T SiPHY OC-192/STM-64 TRANSMITTER Features Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated 16:1 multiplexer and DSPLL™ based clock multiplier unit: Data rates supported: OC-192/STM-64,

GR-253-CORE

Abstract: PRBS31 Si5100 Si5110 Si5320 Si5364
Contextual Info: S i 5 11 0 D A TA S H E E T SiPHY OC-48/STM-16 SONET/SDH T R A N S C E I V E R Features Complete low-power, high-speed, SONET/SDH transceiver integrated limiting amp, CDR, CMU, and MUX/DEMUX. with Si5110 ! ! ! ! ! ! Data rates supported: OC-48/STM-16 through 2.7 Gbps

ap 4604

Abstract: lcd 5421 RD15N rd13n STM-16 STM-64 STS-192 STS-48 TSOT0410G TSOT0410G1
Contextual Info: Advance Data Sheet June 2001 TSOT0410G SONET/SDH STS-192 Overhead and Path Processor Features General • Section, line, and path overhead layer termination for a SONET STS-192 SDH STM-64 or four STS-48 (STM-16) signals. ■ Supports any valid mix of STS-1 and concatenated

SI511

Contextual Info: S i 5 11 0 D A TA S H E E T SiPHY OC-48/STM-16 SONET/SDH T R A N S C E I V E R Features Complete low-power, high-speed, SONET/SDH transceiver integrated limiting amp, CDR, CMU, and MUX/DEMUX. „ „ „ „ „ Data rates supported: OC-48/STM-16 through 2.7 Gbps

83732A

Contextual Info: Agilent 71501C Jitter Analysis System Product Overview A flexible, wide bandwidth jitter analysis system ation/output can be performed at STM-4/OC-12 622 Mb/s , and STM-16/OC-48 (2488 Mb/s)3 rates. Because the system is completely frequency agile, these tests can also be performed at

Contextual Info: Advance Data Sheet September 1999 . . microelectronics group Lucent Technologies Bell Labs Innovations TTRN012G5 2.5 GHz Clock Synthesizer, 16:1 Data Multiplexer Features Description • Fully integrated 2.5 GHz clock synthesizer; 16:1 data multiplexer; supports OC-48/STM-16 data