STD XTL Search Results

Contextual Info: XC2018B Military Logic CelTArray £ XILINX Product Specification. See Note 1. Part Number FEATURES • MIL-STD-883 Class B Processing. Complies with paragraph 1.2.1 • Field-programmable gate array XC2018 • Low power CMOS static memory technology Logic

Contextual Info: XC3042B Military Logic Cell Array Product Specification. See Note 1. FEATURES Part Number • MIL-STD-883 Class B Processing. Complies with paragraph 1.2.1 • Field-programmable gate array XC3042 • Low power CMOS static memory technology Logic Capacity

XC3042B

Abstract: XC3042-PG84 Enplas fpq Enplas 64 pin
Contextual Info: XC3042B Military Logic Cell "Array Product Specification. See Note 1. FEATURES Part Number Logic Capacity gates XC3042 4200 • MIL-STD-883 Class B Processing. Complies with paragraph 1.2.1 • Field-programmable gate array • Low power CMOS static memory technology

Contextual Info: XC2018B Military Logic Cell Array £ X !U N X Product Specification. See Note 1. FEATURES Part Number • MIL-STD-883 Class B Processing. Complies with paragraph 1.2.1 • Field-programmable gate array • Low power CMOS static memory technology Logic Capacity

Contextual Info: Y p o n o n o H XILINX Military Logic Cell Array Product Specification. See Note 1. FEATURES Part Number Logic ConflgCapacity urable gates Logic Blocks User I/Os XC3090 9000 144 • MIL-STD-883 Class B Processing. Complies with paragraph 1.2.1 • Field-programmable gate array

LCA-MEK01

Abstract: 2064 ram
Contextual Info: Military CMOS Programmable Gate Array Logic Cell Array M 2064/M 2018 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CM OS • Low power • T T L or CM OS input threshold levels PROGRAM ABLE • Programmable Logic functions • Programmable I/O blocks

Contextual Info: Military CMOS Programmable Gate Array Logic Cell Array M 2 0 6 4 /M 2 0 1 8 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CMOS • Low power • TTL or CMOS Input threshold levels PROGRAMABLE • Programmable Logic unctions • Programmable I/O blocks

BUS 61555

Contextual Info: QQQ BUS-61555 ILC DATA DEVICI CORPORATION— MIL-STD-1553 ADVANCED INTEGRATED MUX AIM HYBRID FEATU RES PLEASE REFERENCE BUS-61553 DATA SHEET FOR TIMINQ SPECIFICATIONS DESCRIPTION D D C ’s B U S -61 5 5 5 A d va nce d Integrated M ux (A IM ) H y b rid is a c o m p le te MILS T D -1 5 5 3 Bus C on tro lle r (BC), R em ote

M2S050-1FG484I

Abstract: AMBA AXI dma controller designer user guide M2S050-VF400 M2S025-1FG484I d flip flop 7475 M2S010T-1VF400 M2S050-1VF400 M2S025-1VF400I M2S050-1FG896I M2S050
Contextual Info: Revision 0 SmartFusion2 System-on-Chip FPGAs Microsemi’s SmartFusion 2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex -M3 processor, and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most

Contextual Info: Revision 1 SmartFusion2 System-on-Chip FPGAs Microsemi’s SmartFusion 2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex -M3 processor, and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most

flashpro3 schematic

Abstract: TTL XOR2 LVCMOS15 kt 501
Contextual Info: 2 – Device Architecture Fusion Stack Architecture To manage the unprecedented level of integration in Fusion devices, Actel developed the Fusion technology stack Figure 2-1 . This layered model offers a flexible design environment, enabling design at very high and very low levels of abstraction. Fusion peripherals include hard analog IP

B 834 Y

Abstract: uA 741 NC 2N2222 ADG839 LVCMOS15 RAM51 KT 907 ST 1076
Contextual Info: 2 – Device Architecture Fusion Stack Architecture To manage the unprecedented level of integration in Fusion devices, Actel developed the Fusion technology stack Figure 2-1 . This layered model offers a flexible design environment, enabling design at very high and very low levels of abstraction. Fusion peripherals include hard analog IP

flashpro3 schematic

Abstract: LVCMOS15
Contextual Info: 2 – Device Architecture Fusion Stack Architecture To manage the unprecedented level of integration in Fusion devices, Actel developed the Fusion technology stack Figure 2-1 . This layered model offers a flexible design environment, enabling design at very high and very low levels of abstraction. Fusion peripherals include hard analog IP

F5 DIODE

Abstract: class AB2 push pull power amplifier
Contextual Info: Advanced v0.9 Fusion Family of Mixed-Signal Flash FPGAs ® with Optional Soft ARM Support Features and Benefits Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

k 1058 mosfet

Abstract: proton rx 3000 2n3904 h16 yc 428 transistor cx 472
Contextual Info: Advanced v0.8 Fusion Family of Mixed-Signal Flash FPGAs ® with Optional Soft ARM Support Features and Benefits Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

Core8051

Abstract: U1AFS600-FG256 FlashPro3 flashpro3 schematic AES-128 FG256 PQ208 gaa 716 kt 501 PUSH PULL MOSFET DRIVER dip
Contextual Info: Preliminary v0.4 Actel Fusion Mixed-Signal FPGA for the MicroBlade Advanced Mezzanine Card Solution Features and Benefits • Targeted to Advanced Mezzanine Card AdvancedMC Designs • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC)

Contextual Info: Advanced v0.1 Actel Fusion Programmable System Chips for the MicroBlade Advanced Mezzanine Card Solution Features and Benefits On-Chip Clocking Support Targeted to Advanced Mezzanine Card AdvancedMC Designs Designed in Partnership with MicroBlade 8051-Based Module Management Controller (MMC)

actel smart fusion

Contextual Info: Preliminary v0.4 Actel Fusion Mixed-Signal FPGA for the MicroBlade Advanced Mezzanine Card Solution Features and Benefits • Targeted to Advanced Mezzanine Card AdvancedMC Designs • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC)

Contextual Info: November 10, 2008 LMH6517 Multi Standard, IF and Baseband, Dual, DVGA General Description Features The LMH6517 contains two high performance digitally controlled variable gain amplifiers DVGA . It has been designed for use in narrowband and broadband IF sampling applications. Typically the LMH6517 drives a high performance ADC

TBD 234 V12

Abstract: ACM 944 motor IG 2200 19 X 000 15 R
Contextual Info: Advanced v1.2 Actel Fusion Programmable System Chips Mixed-Signal Family with Optional ARM® Support Features and Benefits Low Power Consumption • • High-Performance Reprogrammable Flash Technology • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

zo 103 ma 75 607

Contextual Info: Advanced v1.6 Actel Fusion Mixed-Signal FPGAs ® with Optional ARM® Support Features and Benefits Low Power Consumption • • High-Performance Reprogrammable Flash Technology • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Retains Program when Powered Off

TBD 234 V12

Abstract: op amp ua 745
Contextual Info: Advanced v1.2 Actel Fusion Programmable System Chips ® Mixed-Signal Family with Optional ARM® Support Features and Benefits Low Power Consumption • • High-Performance Reprogrammable Flash Technology • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

Contextual Info: Advanced v1.3 Actel Fusion Programmable System Chips ® Mixed-Signal Family with Optional ARM® Support Features and Benefits Low Power Consumption • • High-Performance Reprogrammable Flash Technology • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

TRANSISTOR KT 838

Abstract: transistor part number 2N2222A 338 2N2222A 2n2222 -331 2n2222 h 331 datasheet
Contextual Info: Revision 0 Actel Extended Temperature Fusion Family of Mixed Signal FPGAs Features and Benefits • Extended Temperature Tested • Each Device Tested from –55°C to 100°C Junction Temperature High-Performance Reprogrammable Flash Technology • • •