STATIC RAM 2048K 70 NS Search Results

Contextual Info: MoBL CY62168DV30 PRELIMINARY 16M 2048K x 8 Static RAM Features power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW . The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1)

Contextual Info: EDI8G322048V White Electronic Designs 2048K x 32 STATIC RAM CMOS, HIGH SPEED MODULE FEATURES DESCRIPTION n 2048K x 32 bit CMOS Static n Random Access Memory n n n Access Times: 20, 25, and 35ns n Individual Byte Selects n Fully Static, No Clocks n TTL Compatible I/O

cd 5151

Abstract: 1MX4 EDI8G322048V EDI8G322048V20MMC DQ28-DQ31
Contextual Info: EDI8G322048V 2048K x 32 Static RAM CMOS, High Speed Module Features DESCRIPTION n 2048K x 32 bit CMOS Static n Random Access Memory The EDI8G322048V is a high speed 64 megabit Static RAM module organized as 2048K words by 32 bits. This module is constructed from sixteen 1024K x 4 Static RAMs in SOJ

32-PIN

Abstract: DS1249AB DS1249AB-100 DS1249AB-70 DS1249Y DS1249Y-100 DS1249Y-70
Contextual Info: DS1249Y/AB 2048k Nonvolatile SRAM www.dalsemi.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation Read and write access times as fast as 70 ns

Contextual Info: MoBL CY62168DV30 PRELIMINARY 16M 2048K x 8 Static RAM Features power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW . The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1)

32-PIN

Abstract: DS1249AB DS1249AB-100 DS1249AB-70 DS1249Y DS1249Y-100 DS1249Y-70
Contextual Info: DS1249Y/AB 2048k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation Read and write access times as fast as 70 ns

28F020T

Abstract: intel 28F020
Contextual Info: 28F020 2048K 256K X 8 CMOS FLASH MEMORY • Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase ■ Quick-Pulse Programming Algorithm — 10 pS Typical Byte-Program — 4 second Chip-Program ■ 100,000 Erase/Program Cycles a 12.0 V ±5% V pp ■ High-Performance Read

Contextual Info: EDI8G322048C 2048K x 32 Static R AM CMOS, High Speed Module RAM FEATURES DESCRIPTION n 2048K x 32 bit CMOS Static n Random Access Memory The EDI8G322048C is a high speed 64 megabit Static RAM module organized as 2048K words by 32 bits. This module is constructed from sixteen 1024K x 4 Static RAMs in SOJ

Contextual Info: CY62168DV30 MoBL 16-Mbit 2048K x 8 Static RAM Features power consumption by more than 99% when deselected Chip Enable 1 (CE 1) HIGH or Chip Enable 2 (CE2) LOW . The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1)

DQ8-DQ11

Abstract: EDI8G322048C static ram 2048K 70 ns
Contextual Info: EDI8G322048C 2048K x 32 Static RAM CMOS, High Speed Module FEATURES DESCRIPTION •2048K x 32 bit CMOS Static The EDI8G322048C is a high speed 64 megabit Static RAM module organized as 2048K words by 32 bits. This module is constructed from sixteen 1024K x 4 Static RAMs in SOJ packages on an epoxy laminate FR4 board.

DS1249AB

Abstract: DS1249Y
Contextual Info: DS1249Y/AB DS1249Y/AB 2048K Nonvolatile SRAM FEATURES PIN ASSIGNMENT • 10 years minimum data retention in the absence of external power NC 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 • Read and write access times as fast as 70 ns A6 6 27

static ram 2048K 70 ns

Abstract: DS1249AB DS1249Y
Contextual Info: DS1249Y/AB DS1249Y/AB 2048K Nonvolatile SRAM FEATURES PIN ASSIGNMENT • 10 years minimum data retention in the absence of external power NC 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 • Read and write access times as fast as 70 ns A6 6 27

Contextual Info: DALLAS DS1249Y 2048K Nonvolatile SRAM s e m ic o n d u c t o r PIN ASSIGNM ENT FEATURES • Data retention in the absence of Vqc I1 1 I1 2 I1 3 I1 4 I1 5 I1 6 II 7 I1 6 I1 9 I1 10 A1 I1 11 AO 11 12 DQO 11 13 DQ1 I1 14 DQ2 I1 15 GND I1 16 NC A16 A14 A12 A7

Contextual Info: D S 1249Y DALLAS SEMICONDUCTOR DS1249Y 2048K Nonvolatile SRAM PIN ASSIGNMENT FEATURES • Data retention in the absence of Vcc • Data is automatically protected during power loss • Replaces 256K x 8 volatile static RAM or EEPROM • Unlimited write cycles

static ram 2048K

Contextual Info: DALLAS s e m ic o n d u c t o r DS1249Y 2048K Nonvolatile SRAM PIN ASSIGNMENT FEATURES • 10 years minimum data retention in the absence of external power Vcc A15 • Data is automatically protected during power loss A17 • Directly replaces 256K x 8 volatile static RAM

32-PIN

Abstract: DS1249Y
Contextual Info: DS1249Y DS1249Y 2048K Nonvolatile SRAM FEATURES PIN ASSIGNMENT • 10 years minimum data retention in the absence of external power NC 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 • Low-power CMOS A6 6 27 A8 • JEDEC standard 32–pin DIP package

Contextual Info: AK5322048BW 2,097,152 Word by 32 Bit CMOS Dynamic Random Access Memory m O C IM T C O R PO m O N DESCRIPTION The Accutek AK5322048BW high density memory module is a CMOS dynamic RAM organized in 2048K x 32 bit words. The mod­ ule consists of four standard 1 Meg x 16 bits DRAMs in plastic SOJ

32-PIN

Abstract: DS1249Y DS1249Y-100 DS1249Y-85
Contextual Info: DS 1249Y DALLAS „ DS1249Y 2048K Nonvolatile S R A M s e m ic o n d u c t o r PIN ASSIGNMENT FEATURES • 10 years minimum data retention in the absence of external power NC I1 1 • Data is automatically protected during power loss A16 I1 A14 I1 • Directly replaces 256K x 8 volatile static RAM

55BVXI

Abstract: CY62168DV30 CY62168DV30L-55BVXI CY62168DV30L-70BVXI CY62168DV30LL-55BVXI
Contextual Info: CY62168DV30 MoBL 16-Mbit 2048K x 8 Static RAM Features addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in

DIP 32 pinout

Contextual Info: ^EDI EDI8M8257C Electronic Designs Inc. • High Speed Two Megabit SRAM Module 256Kx8 Static RAM CMOS, Module Features The EDI8M8257C is a 2048K bit CMOS Static RAM based on two 128Kx8 Static RAMs mounted on a multi­ layered ceramic substrate. Functional equivalence to the monolithic two megabit

Contextual Info: CY62168DV30 MoBL 16-Mbit 2048K x 8 MoBL® Static RAM Features addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in

Contextual Info: AK5322048N 2,097,152 Word by 32 Bit CMOS Dynamic Random Access Memory MICROCIRCUIT CORPORATION DESCRIPTION minimi innmmi The Accutek AK5322048N high density memory module is a CMOS dynamic RAM organized in 2048K x 32 bit words. The module consists of four standard 1 Meg x 16 DRAMs in plastic TSOP

Contextual Info: DS 1249Y DALLAS „ DS1249Y 2048K Nonvolatile SRAM s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • 10 years m inimum data retention in the absence of external power NC I1 1 32 I VCC A16 I1 2 31 A15 A14 I1 3 30 1 At 7 A12 I1 4 29 I WE A7 I1 5 28 I A13

Contextual Info: AK5362048WP 2,097,152 Word by 36 Bit CMOS Dynamic Random Access Memory MICROCIRCUIT CORPORATION DESCRIPTION The Accutek AK53620482WP high density memory module is a CMOS dynamic RAM organized in 2048K x 36 bit words. The module consists of sixteen standard 1 Meg x 4 DRAMs in plastic