STANDARD TTL Search Results

Contextual Info: intei 4289 STANDARD MEMORY INTERFACE • 40 Pin Dual In-Line Package Direct Interface to all Standard Memories Allows Read and Write Program Memory Single Package Equivalent of 4008/4009 TTL Compatible Address, Chip Select, Program Memory Data Lines ■ Standard Operating

Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet High Performance SLX Family Low Power GaAs Standard Cell Arrays Features • Standard Cell Core • Low-Power Macros Available • Five Array Sizes: 10K, 26K, 48K, 72K and 110K Usable Gates • Standard TTL, LVTTL, ECL, LVPECL, GTL,

Contextual Info: MSO Series 5V 9x14mm Surface Mount Crystal Clock Oscillators Œ Œ Œ Œ Œ Œ TTL/CMOS Compatible Anti-Static Tube or Tape & Reel Packaging 1.5 to 40 MHz Frequency Range 40/60% Symmetry Standard 45/55% Symmetry Standard ±100ppm Stability Standard ±50ppm Stability Available

Contextual Info: Voltage Controlled Temperature Compensated Crystal Oscillators SXO-6000C SERIES TTL/CMOS LOGIC VC TCXO SXO-6000C STANDARD SMD VCTCXO STANDARD SPECIFICATIONS H-CMOS VCTCXO Item Part number Frequency range Initial frequency tolerance Frequency stability Temperature range

16R8

Abstract: GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8
Contextual Info: Specifications GAL16LV8ZD GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

16R8

Abstract: GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8
Contextual Info: Specifications GAL16LV8ZD GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

Contextual Info: GAL16LV8ZD Lattica Low Voltage, Zero Power E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

Contextual Info: GAL20LV8ZD Lattica Low Voltage, Zero Power E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

TTL 7414

Abstract: TTL 7414 data 7414 74LS14 function table 7414 hex not 7414 ttl inverter schmitt trigger 7414 7414 equivalent pin configuration 74LS14 ls14
Contextual Info: 7414, LS14 Signetics Schmitt Triggers Hex Inverter Schmitt Trigger Product Specification Logic Products DESCRIPTION The '14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly

74CO4

Abstract: SPICE MODELS ALD1101 ALD SPICE Macromodels FSK11 Design kit SPICE ALD1101 ald1701a dice project ALD1704 74C04 ALD1102
Contextual Info: A PRACTICAL SOLUTION to CUSTOM LINEAR I.C.'s — ALD’s “FUNCTION-SPECIFIC” ASIC PROGRAM “FUNCTION-SPECIFIC” is ALD’s standard cell approach to custom linear circuits with the standard cells being ALD standard products. It allows you to design with completely specified standard linear I.C.’s and implement your custom

74f132 national

Abstract: 54F132DM 54F132FM 54F132LM 74F132PC F132 J14A M14A M14D N14A
Contextual Info: General Description The ’F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In

74ACT14 motorola

Abstract: 74AC ACT14 MC74AC14 MC74ACT14 DSA003657
Contextual Info: MC74AC14 MC74ACT14 Hex Inverter Schmitt Trigger The MC74AC14/74ACT14 contains six logic inverters which accept standard CMOS Input signals TTL levels for MC74ACT14 and provide standard CMOS output levels. They are capable of transforming slowly changing input signals into

GAL20LV8ZD

Abstract: GAL20LV8ZD-15QJ GAL20LV8ZD-25QJ GAL20V8
Contextual Info: Specifications GAL20LV8ZD GAL20LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

Contextual Info: Lattice GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

GAL20LV8ZD

Abstract: GAL20LV8ZD-15QJ GAL20LV8ZD-25QJ GAL20V8
Contextual Info: Specifications GAL20LV8ZD GAL20LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

Contextual Info: GD74F04 PRELIMINARY DATA SHEET HEX INVERTER Description Pin Configuration The GD74F04 contains 6 logic inverters which accept standard TTL input signal and standard TTL output level. They have a greater noise margin than conventional inverters. Vcc 6Y 6A 5Y

GD74F04

Contextual Info: GD74F04 PRELIMINARY DATA SHEET HEX INVERTER Description The GD74F04 contains 6 logic inverters which accept standard TTL input signal and standard TTL output level. They have a greater noise margin than conventional inverters. Pin Configuration Vcc 6Y 6A 5Y

Contextual Info: FEATURES - Long Wavelength - For Singlemode/Multimode Applications - Edge Coupled - Low Power Consumption - Data Rate DC to 5 Mb/s - Standard 5V Power Supply - 4 Pin ST, FC, SP. SC Active Device Mount - Standard TTL Interface RECEIVER CHARACTERISTICS T= 25°C

NEC 2561

Abstract: NEC 2562 NEC 2703 2565 nec GAL20LV8ZD-25QJ GAL20V8 GAL20LV8ZD GAL20LV8ZD-15QJ
Contextual Info: GAL20LV8ZD Features Functional Block Diagram • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices — 50µA Typical Standby Current 100µA Max. — 45mA Typical Active Current (55mA Max.)

Contextual Info: Model 636 HCMOS/TTL CLOCK OSCILLATOR FEATURES • • • • • • • • • • Standard 5.0x3.2mm Surface Mount Footprint HCMOS/TTL Compatible Fundamental and 3rd Overtone Crystals Frequency Range 1.0 – 125 MHz Frequency Stability, ±50 ppm Standard

Contextual Info: AVG Semiconductors DDiT Technical Data DV74LS14 DV74ALS14 Hex Schmitt-Trigger Inverter Each of the six circuits in the DV74LS14/ALS14 contain a logic gate/inverter which accepts standard TTL input signals and provides standard TTL output levels. Each circuit is capable

ic 74132

Abstract: f 74132 LS132 74132 853051 R/ls 74132
Contextual Info: 74132, LS132 SigneHcs Schmitt Triggers Quad 2-Input NAND Schmitt Trigger Product Specification Logic Products The '132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming

Contextual Info: VOLTAGE CONTROLLED CRYSTAL OSCILLATOR F1523BA The Fox F1523BA is a low-cost VCXO. The Fox design meets or exceeds typical industry standard specifications & will also drive 8 TTL loads in the 30 ~ 54MHz range. FEATURES APPLICATIONS • Industry Standard • Pullability

1N43064

Abstract: 1N941 Cal Crystal Lab OR Comclok
Contextual Info: Cal Crystal Lab, Inc./Comclok, Inc. 800-333-9825 TRI-STATE TTL CLOCK OSCILLATORS FULL & HALF SIZE MODEL CU 5.0VDC Model CU CU Frequency Range 10kHz ~ 69.999MHz 70MHz ~ 160.0MHz Frequency Stability 100ppm Standard, Optional Tolerances Available 100ppm Standard, Optional Tolerances Available