STANDARD TTL Search Results
STANDARD TTL Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| 54F151LM/B |
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54F151 - Multiplexer, 1-Func, 8 Line Input, TTL |
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| 93L422ADM/B |
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93L422A - 256 x 4 TTL SRAM |
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| 54F151/BEA |
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54F151 - Multiplexer, 1-Func, 8 Line Input, TTL, CDIP16 - Dual marked (M38510/33901BEA) |
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| 54F573FM/B |
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54F573 - Bus Driver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, |
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| 27S185DM/B |
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27S185 - OTP ROM, 2KX4, 55ns, TTL, CDIP18 |
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STANDARD TTL Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: intei 4289 STANDARD MEMORY INTERFACE • 40 Pin Dual In-Line Package Direct Interface to all Standard Memories Allows Read and Write Program Memory Single Package Equivalent of 4008/4009 TTL Compatible Address, Chip Select, Program Memory Data Lines ■ Standard Operating |
OCR Scan |
MCS-4/40 | |
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Contextual Info: GAL16LV8ZD Lattica Low Voltage, Zero Power E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices |
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GAL16LV8ZD Tested/100% | |
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Contextual Info: GAL20LV8ZD Lattica Low Voltage, Zero Power E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices |
OCR Scan |
GAL20LV8ZD Tested/100% | |
TTL 7414
Abstract: TTL 7414 data 7414 74LS14 function table 7414 hex not 7414 ttl inverter schmitt trigger 7414 7414 equivalent pin configuration 74LS14 ls14
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74f132 national
Abstract: 54F132DM 54F132FM 54F132LM 74F132PC F132 J14A M14A M14D N14A
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ds009477 74f132 national 54F132DM 54F132FM 54F132LM 74F132PC F132 J14A M14A M14D N14A | |
74ACT14 motorola
Abstract: 74AC ACT14 MC74AC14 MC74ACT14 DSA003657
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MC74AC14 MC74ACT14 MC74AC14/74ACT14 MC74ACT14) ACT14 MC74AC14/D* MC74AC14/D 74ACT14 motorola 74AC MC74AC14 MC74ACT14 DSA003657 | |
1N4306
Abstract: 1N941 1N43064
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10kHz 999MHz 70MHz 100ppm -55oC 125oC 999MHz: 1N4306 1N941 1N43064 | |
GD74F04Contextual Info: GD74F04 PRELIMINARY DATA SHEET HEX INVERTER Description The GD74F04 contains 6 logic inverters which accept standard TTL input signal and standard TTL output level. They have a greater noise margin than conventional inverters. Pin Configuration Vcc 6Y 6A 5Y |
OCR Scan |
GD74F04 GD74F04 | |
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Contextual Info: FEATURES - Long Wavelength - For Singlemode/Multimode Applications - Edge Coupled - Low Power Consumption - Data Rate DC to 5 Mb/s - Standard 5V Power Supply - 4 Pin ST, FC, SP. SC Active Device Mount - Standard TTL Interface RECEIVER CHARACTERISTICS T= 25°C |
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MRR135ST/FC/SP/SC | |
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Contextual Info: VOLTAGE CONTROLLED CRYSTAL OSCILLATOR F1523BA The Fox F1523BA is a low-cost VCXO. The Fox design meets or exceeds typical industry standard specifications & will also drive 8 TTL loads in the 30 ~ 54MHz range. FEATURES APPLICATIONS • Industry Standard • Pullability |
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F1523BA F1523BA 54MHz | |
1N43064
Abstract: 1N941 Cal Crystal Lab OR Comclok
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10kHz 999MHz 70MHz 100ppm -55oC 125oC 999MHz: 1N43064 1N941 Cal Crystal Lab OR Comclok | |
schmitt trigger 7413
Abstract: equivalent for 74LS13 PIN CONFIGURATION 74ls13 equivalent for 7413 dual schmitt trigger 7413 4-input nand gate 853051 ttl 7413
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OCR Scan |
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ac14g
Abstract: MC74ACT14
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MC74AC14, MC74ACT14 MC74AC14/74ACT14 MC74ACT14) MC74AC14/D ac14g MC74ACT14 | |
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Contextual Info: MSO Series 5V 9x14mm Surface Mount Crystal Clock Oscillators TTL/CMOS Compatible Anti-Static Tube or Tape & Reel Packaging 1.5 to 40 MHz Frequency Range 40/60% Symmetry Standard 45/55% Symmetry Available ±100ppm Stability Standard ±50ppm Stability Available |
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9x14mm 100ppm 50ppm MIL-STD-883, MIL-STD-202, | |
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Contextual Info: Lattica GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic I Semiconductor I Corporation Functional Block Diagram Features 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices |
OCR Scan |
GAL16LV8ZD Tested/100% | |
10 mhz clock 14 pin dip
Abstract: j-std-020 MXO45HSLV-3C-32M7680 MXO45LV MXO45LV-3C-32M7680
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MXO45LV/MXO45HSLV MXO45LV/MXO45HSLV 2x10-8 J-STD-020. 10 mhz clock 14 pin dip j-std-020 MXO45HSLV-3C-32M7680 MXO45LV MXO45LV-3C-32M7680 | |
mc3487
Abstract: D2578 D2678
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OCR Scan |
MC3487 SLLS098 D2578, RS-422-A MC3487 1N916 1N3064. D2578 D2678 | |
512K32
Abstract: 9Q512K32 UT9Q512 UT9Q512K32
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UT9Q512K32 16Megabit 30krads 300krads 16Mbit) 68-lead 10krad 30krad 512K32 9Q512K32 UT9Q512 | |
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Contextual Info: Standard Products QCOTSTM UT9Q512K32 16Megabit SRAM MCM Data Sheet January 21, 2002 FEATURES q 25ns maximum 5 volt supply address access time q Asynchronous operation for compatible with industry standard 512K x 8 SRAMs q TTL compatible inputs and output levels , three-state |
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UT9Q512K32 16Megabit 50krads 1E-10 68-lead 512K32 -40oC | |
1N941
Abstract: 1N4306 9825
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10kHz 999MHz 70MHz 100ppm -55oC 125oC 999MHz: 1N941 1N4306 9825 | |
MXO45HS
Abstract: mxo45 application notes MXO45 PEAK tray drawing
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MXO45/MXO45HS MXO45/MXO45HS 2x10-8 J-STD-020. MXO45HS mxo45 application notes MXO45 PEAK tray drawing | |
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Contextual Info: Standard Products UT9Q512K32 16Megabit SRAM MCM Advanced Data Sheet March 12, 2001 FEATURES q 35ns maximum 5 volt supply address access time q Asynchronous operation for compatible with industry standard 512K x 8 SRAMs q TTL compatible inputs and output levels, three-state |
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UT9Q512K32 16Megabit 30krads 300krads 8E-11 0E14n/cm2 68-lead -40oC 125oC) 68-pin | |
74LS14 not gate
Abstract: 74LS14 ttl 74ls14 74ls13 74ls14 ttl equivalent for 74LS13 TTL Schmitt-Trigger Inverters TTL Schmitt-Trigger LOW POWER SCHOTTKY 74 LS 14 Logic Gates 74LS14 datasheet
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SN54/74LS13 SN54/74LS14 SN54LS/ 74LS13 SN54LS 74LS14 74LS14 not gate ttl 74ls14 74ls14 ttl equivalent for 74LS13 TTL Schmitt-Trigger Inverters TTL Schmitt-Trigger LOW POWER SCHOTTKY 74 LS 14 Logic Gates 74LS14 datasheet | |
8251 usart architecture and interfacing
Abstract: microprocessors interface 8086 to 8251 2-bit half adder verilog code for 8254 timer
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GSC200 DS4830 8251 usart architecture and interfacing microprocessors interface 8086 to 8251 2-bit half adder verilog code for 8254 timer | |