ST100 DSP Search Results

ST122

Abstract: GP32 1x40 PIN DMC TOOLS AM32 ST100 ST140 soc x1000
Contextual Info: ST122 DSP CORE OVERVIEW HANDBOOK Release 1.0 June 2003 1/54 2/54 TABLE OF CONTENTS ST122 DSP OVERVIEW HANDBOOK TABLE OF CONTENTS PAGE 1 INTRODUCING THE ST100 DSP FAMILY . 6 1.1 MAIN TARGET APPLICATIONS OF ST100 DSP CORES .

PIC dmx example codes

Abstract: fir filter with lms algorithm in vhdl code ST100 dsp vhdl code for FFT 32 point DMX chip 32 bit ALU vhdl code ST140 GP32 32 bit ALU vhdl DMC TOOLS
Contextual Info: ST140 DSP CORE OVERVIEW HANDBOOK Release 1.0 TABLE OF CONTENTS ST140 DSP OVERVIEW HANDBOOK TABLE OF CONTENTS PAGE PREFACE . 7 1 INTRODUCING THE ST100 DSP CORES FAMILY .

decoder huffman

Abstract: huffman encoding Huffman AN1443 ST100 ST120 MEMORY128 ST120DSP
Contextual Info: AN1443 APPLICATION NOTE ST100 VIDEO LIBRARY Baseline JPEG Encoding and Decoding on the ST120DSP By Maurizio Colombo ABSTRACT This application note shows the results of porting the JPEG application for a SW implementation on ST120DSP. JPEG standard is very generic and includes different techniques. The Baseline method is by

30424

Abstract: 31.356 fract16 lgp32 25832 GHS 59 27132 FFT128 30349 AN1444
Contextual Info: AN1444 APPLICATION NOTE General Purpose DSP Library for the ST120 DSP By David DAUBOIS 1 - INTRODUCTION This document presents a set of optimized DSP functions for C programmers on the ST120 DSP. These functions are typically used in real time applications where execution time is critical.

12V relay 4098

Abstract: AD5379 AD5380BST-3 AD5380BST-5 AD5381BST-3 AD5381BST-5
Contextual Info: 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC AD5379 Interface options: Parallel interface DSP/microcontroller-compatible, 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset

ADSP-2185N

Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M D1881 ca144
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

ADSP-2185N

Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M ADSP-2188
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

NLMS Algorithm

Abstract: AN1384 ST120
Contextual Info: AN1384 APPLICATION NOTE Implementing an Acoustic Echo Canceller Algorithm using the ST120DSP By Aude ANDOLFATTO 1 - INTRODUCTION This application note describes an Acoustic Echo Canceller 16 bits, 8KHz, 256ms implementation on the ST120 DSP. The first chapter presents the general principle of an AEC based on the NLMS (Normalized

0x00000088

Abstract: GP32 0x0000008c Trap AN1480 ST100 ST120 ST120-DSP PSR Application Note ST-100
Contextual Info: AN1480 APPLICATION NOTE Handling Traps with the ST120 Core By Béatrice BALAY The first part of this document describes the ST120 Trap Servicing.The second part presents the implemented software to deal with a ’TRAP’ event. Finally, the third part provides the user with a way to

ST140

Abstract: GP32 ST122 ST100
Contextual Info: ST140 ST140 DSP CORE DATA BRIEF 1 • ■ ■ ■ ■ ■ ■ ■ FEATURES Advanced Load/store Architecture – Regular and efficient. – Optimized for programming in ‘C/C+/EC+’ languages. Two Instruction Sets – GP16, a 16-bit instruction set. – GP32, a 32-bit instruction set.

Super10

Abstract: ST10 ST100 ST-100 ST10 microcontroller
Contextual Info: SUPER10 SUPER10 DSP MICROCONTROLLER CORE DATA BRIEF 1 FEATURES • Super10 Key Specifications – Enhanced 16-bit ST10 microcontroller core optimized for real-time performance and System-On-Chip SOC applications (Soft IP) – 300 DSP and MCU Mips – Low power operation: 0.2 to 0.5mW/MHz at

BUTTERFLY DSP

Abstract: eva complex AN1381 ST100 ST120 64 point FFT radix-4 radix-4 asm chart RES02 T02I
Contextual Info: AN1381 APPLICATION NOTE Implementing the Radix-4 FFT Algorithm Using the ST120 DSP By Marianne DELPHIN INTRODUCTION This application note for the ’Radix-4’ implementation of the Fast Fourier Transform algorithm on the ST120 DSP shows how this algorithm well exploits the high parallelism of the ’ST100’ superscalar

AD5382

Abstract: DB10 VOA MEMS BC108 SOT23 package
Contextual Info: 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC AD5382 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode

t54 sot-23

Abstract: AD5380BST-3 AD5380BST-5 AD5383 DB9 pin configuration ST52
Contextual Info: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC AD5383 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode

bc80

Abstract: BC108 characteristic
Contextual Info: 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC AD5381 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down

AD5380BST-5

Abstract: AD5381
Contextual Info: 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC AD5381 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down

Contextual Info: 40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit Voltage Output DAC AD5384 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier

strain guage

Abstract: C3189 4 bit barrel shifter circuit for left shift dsp 32 c processor adsp 218x user manual AD1847 ADSP-2100 ADSP-2181 ADSP2185L ADSP-2185L
Contextual Info: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

BCR 1A11

Abstract: DSP2185
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 19 ns Instruction Cycle Tim e @ 3.3 V olts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2185 FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

AD1847

Abstract: ADSP-2100 ADSP-2181 ADSP2185L ADSP-2185L
Contextual Info: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

Contextual Info: 40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit, Voltage Output DAC AD5384 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier

"analog devices" adsp 2181 and application notes

Abstract: dsp 32 c processor strain guage 0.022 mfd 0.022 mfd capacitor 2 way splitter, circuit diagram DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER AD1847 ADSP-2100 ADSP-2181
Contextual Info: a FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby

AD1847

Abstract: ADSP-2100 ADSP-2181 ADSP2186 ADSP-2186 adsp 2186 EZ-KIT RAM 2186 g 0474 2186B
Contextual Info: a FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby