ST100 DSP Search Results

CORE i3 ARCHITECTURE

Abstract: str 6554 DMC TOOL GP32 ST100 multimedia board core i3 addressing modes str f 6554 DMC 5044 linear handbook ST100
Contextual Info: ST100 DSP-MCU CORE Architecture Overview Handbook ST100 DSP-MCU CORE Architecture Overview Handbook Version 1.1 AZERTY Architecture Overview Handbook I I.1 I.2 I.3 INTRODUCTION THE ST100 CORE ARCHITECTURE ST100 CORE APPLICATIONS ST100 CORE ROADMAP ST100 CORE FEATURES

GHS linker file format

Abstract: ST100 BIT 3713 ST110 GP32 ST120 ST140 ST180 MCU2000
Contextual Info: www.st.com/st100 Version 6.0a - January 2000 page 1  1 CU T S -M P S D TOPICS ST100 Family Overview ST120 Dual MAC Architecture ST120 Implementation ST100 development toolset CU M it -b 6 1 SP U D C it it M -b 6 b 1 32  page 2 ST100 DSP-MCU CORE ST100 Key Advantages.

BIT 3713

Abstract: GP32 ST100 ST100-4W ST1000 MOPS
Contextual Info: ST100: A new DSP-MCU Core Architecture for Embedded Applications Architecture Goals STMicroelectronics’ innovative ST100 DSP-MCU processor core architecture has been conceived specifically for embedded applications in custom system-on-chip products for demanding markets like cellular phones, hard disk drives, engine

ST122

Abstract: GP32 1x40 PIN DMC TOOLS AM32 ST100 ST140 soc x1000
Contextual Info: ST122 DSP CORE OVERVIEW HANDBOOK Release 1.0 June 2003 1/54 2/54 TABLE OF CONTENTS ST122 DSP OVERVIEW HANDBOOK TABLE OF CONTENTS PAGE 1 INTRODUCING THE ST100 DSP FAMILY . 6 1.1 MAIN TARGET APPLICATIONS OF ST100 DSP CORES .

GHS linker

Abstract: ST100 GHS linker file format GHS multi green hills license ST-100 MULTI IDE LINKER C
Contextual Info: ST100 DSP-MCU Core Toolset The ST100 DSP-MCU Core from STMicroelectronics is an innovative new processor core for embedded applications. Based on a 32-bit Load/Store architecture supporting both MCU and DSP code, it replaces a combination of DSP and micro cores in

STMicroelectronics date code format

Abstract: GP32 ST100 dsp ST100 ST120
Contextual Info: ST100 ST100 DSP CORES DATA BRIEF 1 • ■ ■ ■ ■ ■ ■ ■ ■ FEATURES State-of-the-art DSP core architecture – Complete & optimized memory systems – Multicore solutions – Standard or specific tightly coupled peripherals libraries Advanced Load/store Architecture

PIC dmx example codes

Abstract: fir filter with lms algorithm in vhdl code ST100 dsp vhdl code for FFT 32 point DMX chip 32 bit ALU vhdl code ST140 GP32 32 bit ALU vhdl DMC TOOLS
Contextual Info: ST140 DSP CORE OVERVIEW HANDBOOK Release 1.0 TABLE OF CONTENTS ST140 DSP OVERVIEW HANDBOOK TABLE OF CONTENTS PAGE PREFACE . 7 1 INTRODUCING THE ST100 DSP CORES FAMILY .

GP32

Abstract: ST100 integer operation DSP
Contextual Info: STMicroelectronics Innovative new Processor Core for Embedded Applications Combines DSP and Microprocessor Features. Aimed primarily at system-on-chip applications, ST100 DSP-MCU core provides high performance, low power consumption, ease of development and flexibility.

GP32

Abstract: ST100 ST120 ST120-DSP memory bandwidth ST100 multimedia board
Contextual Info: ST Solutions for Embedded Applications ST100 DSP-MCU Cores High Performance DSP-MCU Core 32 bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW

LB598

Abstract: LB156 B0017 ST122 LB807 LB102 B0006 ST100 LB742 LB142
Contextual Info: AN1999 APPLICATION NOTE Tuning C code with the STCC compiler INTRODUCTION The ST100® processor family has been designed to provide a DSP solution that implements the best tradeoff between the following factors: Compiler friendliness. Reduced code size.

decoder huffman

Abstract: huffman encoding Huffman AN1443 ST100 ST120 MEMORY128 ST120DSP
Contextual Info: AN1443 APPLICATION NOTE ST100 VIDEO LIBRARY Baseline JPEG Encoding and Decoding on the ST120DSP By Maurizio Colombo ABSTRACT This application note shows the results of porting the JPEG application for a SW implementation on ST120DSP. JPEG standard is very generic and includes different techniques. The Baseline method is by

evrc

Abstract: ST122 IS-95 MS support evrc AN1997 vocoder implementation ST100 dsp Viterbi Decoder GP32 ST100 ST140
Contextual Info: AN1997 APPLICATION NOTE IS-127 Enhanced Variable Rate Speech Coder EVRC Multi-channel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of the Enhanced Variable Rate Coding (EVRC) vocoder, Speech Service Option 3. This application note also provides a detailed description of the EVRC vocoder multi-channel implemented solution and its performances on to the STMicroelectronics ST122 DSP-MCU system, which is based on the ST100 architecture.

GP32

Abstract: ST100 ST120 bluetooth interfacing design code
Contextual Info: Disk Drive Solutions High Performance DSP-MCU Core 32 bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW Supports arithmetic on 32 bit, saturating, 40 bit extended precision,

GP32

Abstract: ST100 multimedia board ST100 ST120 "vector instructions" saturation
Contextual Info: Disk Drive Solutions High Performance DSP-MCU Core 32-bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW Supports arithmetic on 32-bit, saturating, 40-bit extended precision,

AN1881

Abstract: G711 ST122 G.711 CHIP SET ST100 multimedia evaluation board GP32 ST100 multimedia board ST100 ST140 ST100 dsp
Contextual Info: AN1881 APPLICATION NOTE G711 Speech Codec: Multichannel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of the Multichannel G711 speech codec optimized for performances on the STMicroelectronics STTM ST122 DSP-MCU system, which is

RPE-LTP

Abstract: AN1860 GSM circuit diagram project ST122 ST100 dsp GP32 RPE 113 gsm module with microcontroller ST140 ST100
Contextual Info: AN1860 APPLICATION NOTE GSM 06.10 Full Rate Coder Multi-channel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of the GSM 06.10 Full Rate vocoder. This application note also attempts to provide a description of the GSM 06.10 Full Rate vocoder

lattice codec

Abstract: ST122 gsm circuit diagram project AN1998 GP32 ST100 ST140 VOCODERS voip ST100-DSP
Contextual Info: AN1998 APPLICATION NOTE Half Rate Speech Coder HR Multi-channel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of porting and an optimized implementation of a low bit rate speech coder based on the ETSI GSM-Half Rate (HR) vocoder implementation

30424

Abstract: 31.356 fract16 lgp32 25832 GHS 59 27132 FFT128 30349 AN1444
Contextual Info: AN1444 APPLICATION NOTE General Purpose DSP Library for the ST120 DSP By David DAUBOIS 1 - INTRODUCTION This document presents a set of optimized DSP functions for C programmers on the ST120 DSP. These functions are typically used in real time applications where execution time is critical.

12V relay 4098

Abstract: AD5379 AD5380BST-3 AD5380BST-5 AD5381BST-3 AD5381BST-5
Contextual Info: 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC AD5379 Interface options: Parallel interface DSP/microcontroller-compatible, 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset

Contextual Info: 32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC AD5378 FEATURES Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset

ADSP-2185N

Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M D1881 ca144
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

ADSP-2185N

Abstract: MN1280-R ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

relay 4098

Abstract: 12V relay 4098 T154 AD5378 AD5379ABC AD5380BST-3 AD5380BST-5 AD5381BST-3 AD5381BST-5 BC-108
Contextual Info: 32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC AD5378 Preliminary Technical Data Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option

ADSP-2185N

Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M ADSP-2188
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle