SSTL_3, 3.3 V Search Results

Contextual Info: SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs

1523m

Abstract: MAN09 ICS1523 1523MLFT
Contextual Info: ICS1523 Video Clock Synthesizer with I2C Programmable Delay General Description Features The ICS1523 is a low-cost, high-performance frequency generator. It is well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video

Contextual Info: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB

SN74SSTL16837A

Contextual Info: SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs

SN74SSTL16847

Contextual Info: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB

ICS1523MLF

Abstract: ICS1523 ICS1523M ICS1523MLFT ICS1523MT 132 kv gis
Contextual Info: ICS1523 Video Clock Synthesizer with I2C Programmable Delay General Description Features The ICS1523 is a low-cost, high-performance frequency generator. It is well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video

Contextual Info: SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675F – SEPTEMBER 1996 – REVISED MAY 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs

Contextual Info: SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs

Contextual Info: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A - OCTOBER 1997 - REVISED MAY 1998 * Member of the Texas Instruments Widebus Family • Supports SSTL_3 Signal Inputs and Outputs DGG PACKAGE TOP VIEW I • • • • • [ 1

SN74SSTL16837

Contextual Info: SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675- SEPTEMBER 1996 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Y1 [ 63 A2 GND [ 3 62 GND Y3[ 4 Y4 I 5 61 A3 60 A4 6 V DDQ Y5[ 7 Y6[ 8 59 58 V CC

Contextual Info: HD74SSTL16837 20-bit SSTL_3 Interface Universal Bus Driver with 3-state Outputs HITACHI ADE-205-191 Z Preliminary 1st. Edition July 1, 1997 Description The HD74SSTL16837 is a 20-bit universal bus driver designed for 3.0 V to 3.6 V Vcc operation and SSTL_3 or LVTTL I/O levels.

ICS1524AM

Abstract: ICS1523 ICS1524
Contextual Info: Integrated Circuit Systems, Inc. ICS1524A Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description Features The ICS1524A is a low-cost, very high-performance • frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock

ICS1524

Abstract: ICS1523 metal detector diagram PI
Contextual Info: Integrated Circuit Systems, Inc. ICS1524 Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description Features The ICS1524 is a low-cost, very high-performance frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock

Contextual Info: SN74SSTL16833* 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVE WITH 3-STATE OUTPUTS SCBS675E - SEPTEMBER 1996 - REVISED DECEMBER 199 Member of the Texas Instruments Widebug* Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB

HDMP-2630B

Abstract: HDMP-2631B
Contextual Info: Agilent HDMP-2630B/2631B 2.125/1.0625 GBd Serdes Circuits Data Sheet Description This data sheet describes the HDMP-2630B/2631B serdes devices for 2.125 GBd serial data rates. References to SSTL_2 in the text will also apply to SSTL_3; however, there are separate tables and figures

hp 2631

Abstract: HP 2630 A 2631 hp 2630 datasheet C0603X7R160-104KNE HDMP-2630 A 2631 line receiver HDMP-2631 A 2630 RX-2 -G s
Contextual Info: Agilent HDMP-2630/2631 2.125/1.0625 GBd Serdes Circuits Data Sheet Description This data sheet describes the HDMP-2630/2631 serdes devices for 2.125 GBd serial data rates. References to SSTL_2 in the text will also apply to SSTL_3; however, there are separate tables and figures

Hitachi DSA00101

Abstract: HD74CDC587
Contextual Info: HD74CDC587 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs Preliminary 1st. Edition September 1997 Description The HD74CDC587 is a high-performance, low-skew, low-jitter, phase-locked loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input

Contextual Info: SN74SSTL16837A 20-BIT SSTL 3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C BS 675G - S E P TE M B E R 1996 - R EVISED S E P TE M B E R 1998 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Supports SSTL 3 Signal Inputs and

Contextual Info: HD74CDC587 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs HITACHI Preliminary 1st. Edition September 1997 Description The HD74CDC587 is a high-performance, low-skew, low-jitter, phase-locked loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input

Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

SY55857L

Abstract: SY55857UKI SY55857UKITR
Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

Contextual Info: CDC587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS562B- DECEMBER 1996 - REVISED JULY 1998 DQG PACKAGE TOP VIEW • Operates at 3.3-V Vqc • Distributes One Clock Input to 16 Outputs • Four Select Inputs Configure Output

Contextual Info: CDC2587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS560B - DECEMBER 1996 - REVISED JULY 1996 • • • • • • • DQQ PACKAGE TOP VIEW CLKIN VREF FBIN Vcc FBOUT GND Vcc 1Y0 1Y1 GND VCC 1Y2 1Y3 GND V cc 2Y0 2Y1 GND V cc

CC33G

Contextual Info: CDC587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCASS62B - DECEMBER 1996 - REVISED JULY 1996 Low-Output Skew and Jitter for Clock Distribution and Synchronization DOG PACKAGE TOP VIEW CLKIN [ 1 u v refÌ 2 FBIN [ 3 Veci 4 FBOUT [ 5