SSTL IO PAD Search Results

PLL 4046 4011 4017

Abstract: phase angle controller SIII52001-1 SSTL-15 SSTL-18
Contextual Info: Stratix III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V2-1.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

PLL 4046 4011 4017

Abstract: 5252 F 1107 SSTL-15 SIII52001-1 SSTL-18 4046 PLL Designers Guide 0906NS DDR SDRAM Controller VCO 1430 2230 MHz
Contextual Info: 1. Stratix III Device Datasheet: DC and Switching Characteristics SIII52001-1.3 Electrical Characteristics Operating Conditions When Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible

PC3200

Contextual Info: IDT74SSTVN16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE IDT74SSTVN16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • • 1:2 registered output buffer 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

PC3200

Contextual Info: IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTVF16859 ADVANCE INFORMATION DESCRIPTION: • • • • • • • 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700

SSTL IO pad

Abstract: d1064 IDT74SSTVN16859C PC2100 PC2700 PC3200
Contextual Info: IDT74SSTVN16859C 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED IDT74SSTVN16859C BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 1:2 registered output buffer 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

Contextual Info: IDT74SSTVM16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED IDT74SSTVM16859 BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 1:2 register buffer Meets or exceeds JEDEC standard SSTVM16859

IDT74SSTV16859

Abstract: Q11A Q13A SSTV16859
Contextual Info: IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTV16859 DESCRIPTION: • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs

H.264 encoder cortex a8

Abstract: arm cortex a9 cortex-a9 CMOS Sensor 1080p H.264 60 android mobile MOTHERBOARD CIRCUIT diagram 667 transistor ecb CHINA TV uoc ARm cortexA9 GPIO android mobile circuit diagram "ARM Cortex A9"
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

arm cortex a9

Abstract: H.264 encoder cortex a8 "ARM Cortex A9" cmos digital camera module MMC 4.2 "NOR Flash controller" H.264 codec PD46 Dual-core ARM Cortex-A9 CPU cortex-a9
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − production data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

Contextual Info: IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs

IDT74SSTV16859

Abstract: Q11A Q13A SSTV16859
Contextual Info: IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16859 PRELIMINARY 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • The SSTV16859 is a 13-bit to 26-bit registered buffer designed for 2.3V2.7V VDD and supports low standby operation. All data inputs and outputs

alan 100 plus

Abstract: Microwave PIN diode spice power supply diagram
Contextual Info: DesignCon 2007 FPGA Design for Signal and Power Integrity Larry Smith, Altera Corporation Hong Shi, Altera Corporation CP-01023-1.0 January 2007 Abstract FPGAs have traditionally been optimized for low-cost environments where signal and power integrity are minor considerations. With today’s requirements for high-speed

LGA 2011 Socket diagram

Abstract: BR17
Contextual Info: Intel Core i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 1 Supporting Desktop Intel® Core™ i7-3960X and i7-3970X Extreme Edition Processor for the LGA-2011 Socket Supporting Desktop Intel® Core™ i7-39xxK and i7-38xx Processor Series

zx 15 itt

Abstract: CIII52001-3 EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 SSTL-18 EP3CLS70
Contextual Info: Section 1. Cyclone III Device Data Sheet This section includes the following chapter: • Chapter 1, Cyclone III Device Data Sheet ■ Chapter 2, Cyclone III LS Device Data Sheet Revision History Refer to each chapter for its own specific revision history. For information on when

Contextual Info: April 2008 HYB25D128160C[E/T] HYB25D128400C[C/E/T] HYB25D128800C[C/E/F/T] 128-Mbit Double-Data-Rate SDRAM DDR SDRAM Internet Data Sheet Rev. 1.70 Internet Data Sheet HYB25D128[40/80/16]0C[C/E/F/T] 128-Mbit Double-Data-Rate SDRAM Revision History: Rev. 1.70, 2008-04

CIII52001-3

Abstract: EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 SSTL-18 1085 fm transmitter
Contextual Info: Cyclone III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com CIII5V2-3.3 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: March 2008 HYB25DC256803C[E/F] HYB25DC256163C[E/F] 2 5 6 - M b i t D o u b l e - D a t a - R a t e SG R A M Green Product Internet Data Sheet Rev. 1.30 Internet Data Sheet HYB25DC256[80/16]3C[E/F] 256-Mbit Double-Data-Rate SGRAM HYB25DC256803C[E/F], HYB25DC256163C[E/F]

SPRS717

Abstract: S-PBGA-N324 S-PBGA-N298 powervr 544 GPMC IEEE1500 PowerVR sgx GPMC OMAP NAND ARM v7 CORTEX-A8 DDRA15
Contextual Info: AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717 – OCTOBER 2011 www.ti.com AM335x ARM Cortex -A8 Microprocessors MPUs Check for Samples: AM3359, AM3358 1 Device Summary 1.1 Features • Highlights – 500-MHz, 600-MHz, or 720-MHz ARM® Cortex™-A8 32-Bit RISC Microprocessor

Multi-Effects Audio Processor

Abstract: SAM3303 ATSAM3703 delay reverb diagram schematic "pitch shifter" "pitch shifter" ic remix motor start capacitors SAM97XX 10band graphic equalizer Equalizer delay reverb
Contextual Info: Features • • • • • • • • • • • • • • • • • Three DSPs and 24-bit Audio Router On-chip 32 kHz to 96 kHz Sampling Rate Enhanced P16 Processor with C Compiler New 48-bit Double-precision DSP Instructions Built-in 16K x 16 Flash Memory

msc251

Abstract: msc250 MSC-251
Contextual Info: MagnaChip Semiconductor Library Team MSC250/251 Description MSC250/251 library is 0.25-micron cell base library which supports 3LM, 4LM, 5LM and stacked vias to enable extremely high density. MSC250/251 library is suitable for today’s complex design requirements including small

atmel h020

Abstract: atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
Contextual Info: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates

atmel h020

Abstract: atmel 0713 AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 usb 3 sm Flash drive controller M25Pxxx state machine for ahb to apb bridge
Contextual Info: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates

811b transistor

Abstract: 11bl 811b
Contextual Info: Low Skew, 1-to-2, Differential-to-CML Fanout Buffer ICS858011 NRND NRND – Not Recommend for New Designs PRELIMINARY DATASHEET Product Discontinuance Notice – Last Time Buy Expires on 6/22/2013 General Description Features The ICS858011 is a high speed 1-to-2 Differential-to-CML Fanout

OPP120

Abstract: 15.4" WXGA 1366x768 GPIO0-12 15.4 1366x768 S-PBGA-N324 SPRUH73 JESD209B JESD79-2F
Contextual Info: AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717A – OCTOBER 2011 – REVISED JANUARY 2012 www.ti.com AM335x ARM Cortex -A8 Microprocessors MPUs Check for Samples: AM3359, AM3358 1 Device Summary 1.1 Features • Highlights – 275-MHz, 500-MHz, 600-MHz, or 720-MHz