SRAM READ/WRITE CIRCUIT Search Results

MR2A08AMYS35

Abstract: AECQ-100 MR2A08AYS35 BGA 8 x 8 tray MR2A08A
Contextual Info: MR2A08A FEATURES 512K x 8 MRAM Memory • Fast 35ns Read/Write Cycle • SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign • Unlimited Read & Write Endurance • Data Always Non-volatile for >20-years at Temperature • One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in

MR2A16AC

Abstract: tsop 48 PIN type2 MR2A16AMY MRAM MR2A16ACYS35R 44TSOP mr2a16amys35 MR2A16ATS35 MR2A16A 012MAX
Contextual Info: MR2A16A FEATURES 256K x 16 MRAM Memory • Fast 35 ns Read/Write Cycle • SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign • Unlimited Read & Write Endurance • Data Non-volatile for >20-years at Temperature • One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in

M48Z35

Abstract: M48Z35Y SOH28
Contextual Info: M48Z35 M48Z35Y 256 Kbit 32Kb x8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION ■ WRITE PROTECT VOLTAGES

Contextual Info: M48Z08 M48Z18 5 V, 64 Kbit 8 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection

Contextual Info: M48Z02 M48Z12 5 V, 16 Kbit 2 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection

DS1225

Abstract: M48Z08 M48Z18 THE M48Z
Contextual Info: M48Z08 M48Z18 5V, 64 Kbit 8Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM AND POWER-FAIL CONTROL CIRCUIT UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION

CY7C15632KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

Contextual Info: M48Z35 M48Z35Y 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION ■

M48Z35AV

Abstract: M48Z35AY SOH28
Contextual Info: M48Z35AY M48Z35AV 256 Kbit 32Kb x8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ BATTERY LOW FLAG (BOK) ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb4 SRAM 36Mb QDR SRAM 4-WORD BURST MT54V2MH18E MT54V1MH36E Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE

CY7C2263KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports

Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions

DS1225

Abstract: M48Z08 M48Z18 M4Z28-BR00SH SOH28 DS1225 equivalent
Contextual Info: M48Z08 M48Z18 5V, 64 Kbit 8Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, and POWER-FAIL CONTROL CIRCUIT ■ UNLIMITED WRITE CYCLES ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ ■ ■ AUTOMATIC POWER-FAIL CHIP DESELECT

MR0A08BC

Abstract: MR0A08BCYS35
Contextual Info: MR0A08B FEATURES 128K x 8 MRAM • 3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Native non-volatility • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • Commercial and industrial temperatures

MR4A16B

Abstract: MR4A16BCMA35 MR4A16BCYS35 54TSOP2 MR4A16BCYS35R 54-TSOP2 MR4A16BMA35R MR4A16BC aecq100
Contextual Info: MR4A16B FEATURES 1M x 16 MRAM • +3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant small footprint BGA and TSOP2 package

32-KW Load Bank

Abstract: tes 1310 LFBGA 555H SST34HF324G
Contextual Info: 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory Data Sheet FEATURES: • Flash Organization: 2M x16 – 32 Mbit: 24Mbit + 8Mbit • Concurrent Operation – Read from or Write to SRAM while

CY7C1512KV18-250BZXI

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

M48Z35AV

Abstract: M48Z35AY M4Z28-BR00SH1 SOH28
Contextual Info: M48Z35AY M48Z35AV 5.0 or 3.3V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ BATTERY LOW FLAG (BOK) ■ AUTOMATIC POWER-FAIL CHIP DESELECT

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

CY7C1612KV18

Contextual Info: CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9

CY7C1412KV18-250BZXC

Abstract: CY7C1425KV18 CY7C1412KV18-250BZC CY7C1414KV18
Contextual Info: CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 36-Mbit QDR II SRAM 2-Word Burst Architecture 36-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1425KV18 – 4 M x 9

TR321

Contextual Info: m MX66V2000 A Low Power/Voltage 512k x 8 CMOS SRAM FEATURES DESCRIPTION QJ Wide operation voltage 2.4V ~ 5.5V O Low power consumption Vcc=3.0V 20mA Max. write current 2mA (Max.) read current luA (Typ.) CMOS standby cuirent Vcc=5.0V 30mA (Max.) write current

555H

Abstract: BKX555H SST34HF3244C
Contextual Info: 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C SST34HF32x4x32Mb CSF + 4/8/16 Mb SRAM x16 MCP ComboMemory Data Sheet FEATURES: • Flash Organization: 2M x16 or 4M x8 • Dual-Bank Architecture for Concurrent Read/Write Operation – 32 Mbit Top Sector Protection