SRAM 1987 Search Results

E 13007-1

Abstract: 13007 h3 detail of D 13007 K 13007 he 13007-1 SE 13007 SEC 13005 13005 2 E 13007 sec 13007
Contextual Info: Ml L-H-38510/610 25 FEB R U A R Y 1987 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, VHSIC, CMOS, 65,536-BIT SELECTABLE MODE, STATIC RANDOM ACCESS MEMORY SRAM , MONOLITHIC SILICON This specification Is approved for use by all Depart­ ments and Agencies of the Department of Defense.

hm3-65764

Abstract: 65764 65764 ram
Contextual Info: T-46-23-12 HM 65764 8K x 8 HIGH SPEED CMOS SRAM OCTOBER 1987 Features • • • • • • • • FAST ACCESS TIME : 35/45/55 ns max STANDBY CURRENT : 20 mA OPERATING CURRENT : 150 mA ASYNCHRONOUS INPUTS TTL COMPATIBLE INPUTS AND OUTPUTS SINGLE 5 VOLT SUPPLY

28F6408J3

Abstract: 28F6408J3A Intel SCSP
Contextual Info: 3 Volt Intel StrataFlash Memory Stacked-CSP 28F6408J3 Preliminary Datasheet Product Features • ■ ■ ■ ■ ■ ■ Flash Memory plus SRAM — Reduces Memory Board Space Required, Simplifying PCB Design Complexity Stacked Chip Scale Package Technology

winband

Abstract: W25X40BV W25Q408W w25x40v W651GG2JB WSON* 8x6mm w25q128 W25X16AV 208-MIL w25X20BV
Contextual Info: t/vinband We D eliver Product Selection Guide - o 2010 Mobile RAM Specialty DRAM Graphics DRAM Flash Memory Memory Product Foundry Service Product Selection Guide 2010 Contents 2 Mobile RAM Pseudo SRAM Low Power SDR SDRAM Low Power DDR / DDR2 SDRAM

Contextual Info: MOSEL 1K X 8 CMOS DUAL PORT SRAM MS6130/40 January 1987 FEATURES DESCRIPTION • • The MOSEL MS6130 and MS6140 are 8,192 bit dual port static random access memory organized as 1,024 words by 8 bits. The MS6130 is designed to be used as a stand-alone 8 bit dual-port RAM or as a “MASTER”

MS6130L-90PDC

Abstract: AC1237
Contextual Info: r , MOSEL ' 1K X 8 CMOS DUAL PORT SRAM MS6130/40 i . \ January 1987 DESCRIPTION FEATURES • • High-speed— 55/70/90ns Max. Low Power dissipation 325mW (Typ.) Operating 5 |j,W(Typ.) Standby •^ S in g le 5V power supply • Fully static operation • All inputs and outputs directly TTL compatible

CL100 transistor

Abstract: transistor E 13009 1024x4 bit ram transistor cl100 if6 hall 13009 TRANSISTOR equivalent gm f131 13005 TRANSISTOR HALL EFFECT TRANSISTOR 17S IAIO 3Y
Contextual Info: MIL-M-38510/245A 28 January 1987 _ s u p e r s iin r MIL-H-38510/2455 USAF 5 April 1983 " m ilit a r y spec ific a t io n MICROCIRCUITS, DIGITAL. CMOS, 4096 BIT, STATIC RANDOM ACCESS MEHORY SRAM), BULK SILICON AND SILICON 0# SAPPHIRE This specification 1s approved f ° r use

a13914

Abstract: DIL-22
Contextual Info: ^ T-46-23-10 HM 65788 16K x 4 HIGH SPEED CMOS SRAM O C T O B E R 1987 Pinouts Features • • • • • • • • FAST ACCESS TIME : 25/35/45 ns STANDBY CURRENT : 15 mA OPERATING CURRENT : 100 mA ASYNCHRONOUS INPUTS TTL COMPATIBLE INPUTS AND OUTPUTS SINGLE 5 VOLT SUPPLY

AM29030

Abstract: M68040
Contextual Info: V292BMC Rev D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 AND M68040/60™ PROCESSORS BLOCK DIAGRAM • Direct interface to Am29030/40 processors • Designed to work with V292PBC/V360EPC PCI bridge • Near SRAM performance achieved with DRAM

Contextual Info: SAMSUNG ELECTRONICS INC b?E T> 7 *îb4 m s 0P17S1S bSO • SMGK PRELIMINARY BiCMOS SRAM KM68B261A ABSOLUTE MAXIMUM RATINGS* Item Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to VSs Power Dissipation Storage Temperature Operating Temperature

Contextual Info: Integrated Device Technolog y Inc 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, LATCHED /BUFFERED DATA!N LINES AND REGISTERED DATA out LINES FEATURES: • Registered address lines • Latched and Buffered Input data lines • Registered output data lines • Separate I/O

W25X128

Abstract: W25Q40 w25q64 W25Q16BW W25Q64bv W25X80BV W25Q32BV W25016BV winbond* W25Q W25X16AV
Contextual Info: winband We D eliv er 2009 Product Selection Guide Mobile RAM Specialty DRAM Flash Memory Memory Product Foundry Service O W Product Selection Guide 2009 » Contents 2 Mobile RAM Pseudo SRAM Low Power SDR SDRAM Low Power DDR SDRAM 4 Specialty DRAM SDRAM DDR SDRAM

Signal Path Designer

Contextual Info: V96BMC Rev D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960 Cx/Hx/Jx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Direct interface to i960Cx/Hx/Jx processors • 2Kbyte burst transaction support • SRAM performance achieved with DRAM • Designed to work with V961PBC and

C3264

Abstract: RAM-6A
Contextual Info: 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, REGISTERED DATA|N LINES AND LATCHED/BUFFERED DATA0UT LINES IDT7M822 CS and WE data that meets the specified set-up time will be latched when LE goes low. DATA in is controlled by its own clock, CPDIN. When ENDIN

Contextual Info: INT EG RAT ED DEVICE T7 dË J 482577 1 INTEGRATED DEVICE MÖHS771 ODOSÖDÜ 4 97D 0 2800 T -4 6 -2 3 -1 4 Integrated DeviceTechnology Inc. 128K x 8 SRAM WITH REGISTERED IDT7M826 ADDRESS LINES, REGISTERED DATA.m LINES AND LATCHED/BUFFERED DATA0UT LINES 53

Contextual Info: SAMSUNG ELECTRONICS INC b7E D • 7 ^ 4 1 4 5 0017STÌ 27b ■ SHGK PRELIMINARY K M 6 8 B 2 6 1 A _ BiCMOS SRAM TIMING WAVEFORM OF WRITE CYCLE C S C ontrolled - t w c (2) - jC - tWR -tew - 'tAW " ) ) ) ) ) ' A -t o w - -t w z (3,4,5)-

SC700

Contextual Info: INTEGRATE» DEVICE T7 D E I 4Ö25771 0002700 7 482577 1 INTEGRATED DEVICE 97D 02788 " 128K X 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES AND REGISTERED DATA LINES D IDT7M821 Address, Write Enable W E and the three Chip Select (CS) lines are controlled by LE. When LE is'hlgh, the address latches

C3264

Contextual Info: INT EGR AT ED DEVICE T7 4 8 2 5 7 7 1 I NTEGRATED Integrated DeviceTechn0t03y. Inc. D E | 4ÖSS771 DDOaflDB 0 | DE V I C E 97D 02803 ^- T -4 6 -2 3 -1 4 IDT7M827 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, LATCHED /BUFFERED DATA!N LINES AND REGISTERED DATA0Ut l,NES

hmt design

Abstract: 5HM1 HM1-65788 HM65789
Contextual Info: T -4 6 -2 3 -1 0 HM 65789 16K x 4 HIGH SPEED CMOS SRAM OCTOBER 1987 Pinouts Features • • • • • • • • • A5 A6 A7 Aß A9 AIO A lt Ai2 A13 CS C1 C2 L3 C4 C5 ÔË C 6 7 B 9 10 tl GND C 12 C C n C C LCC 28 PINS 24 3 VCC 23 3 A4 22 3 A3 21 3 A2

Contextual Info: INTEGRATE» DEVICE T7 dËJ 4ÖSS771 DDD a7û 5 1 |~~ 97D 027 85 482577 1 INTEGRATED DEVICE D T -4 6 -2 3 -1 4 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES AND LATCHED/BUFFERED DATA LINES IDT7M820 Integrated Devicelechnotogy. Inc DATAin Is controlled by Its own enable, LEDIN. With this line In

Contextual Info: i 128K x 8 SRAM WITH REGISTERED ADDRESS LINES AND LATCHED/ BUFFERED DATA LINES IDT7M828 integrated Device Technology. Inc Address, Write Enable W E an_d the three C hip Select (CS) lines are controlled by CP. W hen C E (clock enable) is asserted, all address, C S a n d W E datathatm eetsthesp eclfled set-up tim ew ill

IDT7198

Contextual Info: INTEGRATE» DEVICE T7 4825771 I NTEGRATED D Ë J ^1055771 00027^1 97D DE V I C E 02791 D T-46-23-14 Integrateci DeviceTêchnok^y. Inc. 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, REGISTERED DATAm LINES AND LATCHED/BUFFERED DATA0Ut LINES CS and WE data that meets the specified set-up time will be

Contextual Info: I Integrated Dev ice le ch n o lo g y. Inc 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, LATCHED/BUFFERED DATAm LINES AND REGISTERED DATA0U TLlNES IDT7M823 D A T A i n is controlled by its own enable, LEDIN. With this line in the high state, the latch is in the transparent or buffer mode. All

Contextual Info: 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, REGISTERED DATA!N LINES AND LATCHED/BUFFERED DATA o u t LINES Address, Write Enable W E and the three Chip Select (CS) lines are controlled by CP. W hen CE (clock enable) is asserted, all address, C S a n d W E data that m eetsthe specified set-up time will