54ACT110 Search Results

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

tl401

Contextual Info: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible

Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout

D2957

Abstract: 1987-REVISEDAPRIL
Contextual Info: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted

ti0041

Contextual Info: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES T I0041— D2957, JUNE 1967— REVISED M ARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 00 . . . J P ACKA G E 7 4 A C T 1 1000 . . . D O R N PACKA GE • Flow-Through Architecture to Optimize PCB

74ACT11086

Contextual Info: 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES T 10185— D3390, N O VEM BER 1969 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout TOP VIEW

Contextual Info: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout

Contextual Info: 54ACT11021, 74ACT11021 DUAL 4ĆINPUT POSITIVEĆAND GATES ą ą SCAS012B − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • 54ACT11021 . . . J PACKAGE 74ACT11021 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes

Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - D2957, JUNE 1987 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible ■ ■ * Flow-Through Architecture to Optimize PCB Layout I I * Center-Pin V^c and GND Configurations to Minimize High-Speed Switching Noise

54ACT11010

Abstract: 74ACT11010 D2957
Contextual Info: 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

54ACT11002

Abstract: 74ACT11002 D2957
Contextual Info: 54ACT11002, 74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A – D2957, JUNE 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations

74ACT11034

Abstract: 54ACT11034 D2957
Contextual Info: 54ACT11034, 74ACT11034 HEX NONINVERTERS SCAS035A – D2957, FEBRUARY 1988 – REVISED APRIL 1993 • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

54ACT11011

Abstract: 74ACT11011 D2957 vqc 10 C
Contextual Info: 54ACT11011, 74ACT11011 TRIPLE 3-INPUT POSITIVE-AND GATES TI0051— D2957. JULY 1987— REVISED MARCH 1990 54ACT11011 . . . J PACKAGE 74ACT11011 . . . D OR N PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout TOP VIEW

54ACT11034

Abstract: 74ACT11034 D2957
Contextual Info: 54ACT11034, 74ACT11034 HEX NONINVERTERS TI0063— D2957, FEBRU ARY 198ft— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11034 . . . J PACKAGE 74ACT11034 . . . DW OR N PACKAGE Flow-Through Architecture to Optimize PCB Layout o D1A 19 18 17

54ACT11030

Abstract: 74ACT11030 74ACT11030DR
Contextual Info: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout

54ACT11020

Abstract: 74ACT11020 D2957
Contextual Info: 54ACT11020, 74ACT11020 DUAL 4ĆINPUT POSITIVEĆNAND GATES ą ą SCAS016A − D2957, JUNE 1987 − REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to

74ACT11027

Abstract: 54ACT11027 D2957
Contextual Info: 54ACT11027, 74ACT11027 TRIPLE 3-INPUT POSITIVE-NOR GATES SCAS020A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • 54ACT11027 . . . J PACKAGE 74ACT11027 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes

Contextual Info: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS002A – D2957, JUNE 1987 – REVISED APRIL 1993 • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

54ACT11011

Abstract: 74ACT11011 D2957
Contextual Info: 54ACT11011, 74ACT11011 TRIPLE 3-INPUT POSITIVE-AND GATES SCAS028A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 54ACT11004,74ACT11004 HEX INVERTERS SCAS215 - D2957, JANUARY 1988 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Performance Implanted

Contextual Info: 54ACT11021, 74ACT11021 DUAL 4-INPUT POSITIVE-AND GATES SCAS012B - P2957, JULY 1978 - REVISED APRIL 1993 54ACT11021 . . . J PACKAGE 74ACT11021 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GND Configurations

U2-15

Contextual Info: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0065— D2957, DECEM BER 198«— R EVISED MARCH 1990 54ACT11074 . . . J PACKAGE 74 ACT 11074 . . . D O R N PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB

Contextual Info: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES T10061— D2957, JULY 1987—REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 32 . . . J P ACKA G E 7 4 A C T 11 0 32 . . . O OR N P ACKA G E • Flow-Through Architecture to Optimize PCB

Contextual Info: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008B-D2957, JULY 1987-REVISEDAPRIL1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Oenter-PIn V^c and GND Configurations to Minimize High-Speed Switching Noise