SQA64A Search Results

LMK04828BISQE

Abstract: LMK04828B
Contextual Info: LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04826B, LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support

ADC16V130CISQ

Abstract: MABACT0040
Contextual Info: ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs General Description The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second MSPS . This converter uses a differential,

varactor 650 manual

Contextual Info: LMK04906 www.ti.com SNAS589C – NOVEMBER 2011 – REVISED DECEMBER 2012 LMK04906 Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs Check for Samples: LMK04906 FEATURES APPLICATIONS • • • 1 23 • • • • • • • •

Contextual Info: LMK04828B www.ti.com SNAS605 AO – MARCH 2013 – REVISED MARCH 2013 LMK04828 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support • Ultra-Low RMS Jitter and Performance

Contextual Info: LMK04800 www.ti.com SNAS489J – MARCH 2011 – REVISED MARCH 2013 LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04800 1 FEATURES 123 • Ultra-Low RMS Jitter Performance – 111 fs RMS Jitter 12 kHz to 20 MHz – 123 fs RMS Jitter (100 Hz to 20 MHz)

LMK04828B

Contextual Info: LMK04828B www.ti.com SNAS605 AO – MARCH 2013 – REVISED MARCH 2013 LMK04828 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support • Ultra-Low RMS Jitter and Performance

Contextual Info: LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04826B, LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support

MLT 22 MOSFET AUDIO AMPLIFIER

Abstract: Hdmi to micro usb wiring diagram LM2687LDX LMS4684LD transistor SMD 12W inverter hdmi CONVERTER SDI IC CAT-5 Sdi IC ADC081S021CISD ds15br400 DP83848k
Contextual Info: DP83848K PHYTER Mini LS Industrial Temperature Single Port 10/100 Ethernet Transceiver General Description Features The DP83848K addresses the quality, reliability and small • Low-power 3.3V, 0.18µm CMOS technology form factor required for space sensitive applications in • Auto-MDIX for 10/100 Mb/s

PS 1025

Abstract: Power Supply Control IC dap 07 LMK04828B LMK04828
Contextual Info: LMK04828B www.ti.com SNAS605 AO – MARCH 2013 – REVISED MARCH 2013 LMK04828 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support • Ultra-Low RMS Jitter and Performance

Contextual Info: ADC16V130 www.ti.com SNAS458E – NOVEMBER 2008 – REVISED MARCH 2013 ADC16V130 16-Bit, 130 MSPS A/D Converter With LVDS Outputs Check for Samples: ADC16V130 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • • Dual Supplies: 1.8V and 3.0V Operation

VXB1-1137-15M360

Abstract: 38.88 NF 820 OLT block diagram GPON VXB1
Contextual Info: LMK03806 www.ti.com SNAS522H – SEPTEMBER 2011 – REVISED AUGUST 2012 LMK03806 Ultra Low Jitter Clock Generator with 14 Programmable Outputs Check for Samples: LMK03806 FEATURES 1 • 2 • • • • • • • High Performance, Ultra Low Jitter Clock

226 varactor

Contextual Info: TI Confidential - NDA Restrictions LMK04906 www.ti.com SNAS589B – NOVEMBER 2011 – REVISED DECEMBER 2012 LMK04906 Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs Check for Samples: LMK04906 FEATURES APPLICATIONS • • • 1

SQA64A

Abstract: JESD204B JESD-20
Contextual Info: LMK04820 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs 1.0 General Description 3.0 Features The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The dual loop PLLatinum architecture enables sub-100 fs RMS jitter

SNAS605

Abstract: LMK04828 PS 1025 LMK04828B 0X158
Contextual Info: LMK04828B www.ti.com SNAS605 AO – MARCH 2013 – REVISED MARCH 2013 LMK04828 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support • Ultra-Low RMS Jitter and Performance

Contextual Info: ADC16V130 www.ti.com SNAS458E – NOVEMBER 2008 – REVISED MARCH 2013 ADC16V130 16-Bit, 130 MSPS A/D Converter With LVDS Outputs Check for Samples: ADC16V130 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • • Dual Supplies: 1.8V and 3.0V Operation

DAP 07

Abstract: JESD22-B111 DAP 08 transistor smd sensor 80L dap 07 smd dap sot 23-5 SPA52A AN-1187 LQB08A MO-220
Contextual Info: National Semiconductor Application Note 1187 August 27, 2010 Table of Contents Introduction . 2 Package Overview . 2

vrm circuit testing

Abstract: VA-30
Contextual Info: ADC16V130 ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs Literature Number: SNAS458D ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs General Description The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input

Contextual Info: ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs General Description The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second MSPS . This converter uses a differential,

Contextual Info: LMK04820 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs 1.0 General Description 3.0 Features The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The dual loop PLLatinum architecture enables sub-100 fs RMS jitter

solid state 220 volt stabilizer circuit

Abstract: national semiconductor MDAC VDR RESISTOR MABACT0040 ADC16V130CISQ single phase automatic stabilizer using transformer
Contextual Info: ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs General Description The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second MSPS . This converter uses a differential,

LMK04800

Abstract: LMK0480X
Contextual Info: LMK04800 www.ti.com SNAS489J – MARCH 2011 – REVISED MARCH 2013 LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04800 1 FEATURES 123 • Ultra-Low RMS Jitter Performance – 111 fs RMS Jitter 12 kHz to 20 MHz – 123 fs RMS Jitter (100 Hz to 20 MHz)

Contextual Info: LMK04816 www.ti.com SNAS597B – JULY 2012 – REVISED APRIL 2013 LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04816 1 Introduction 1.1 FEATURES 123 • Ultra-Low RMS Jitter Performance – 100 fs RMS Jitter 12 kHz to 20 MHz

CVHD-950-122

Abstract: K0490
Contextual Info: LMK04906 www.ti.com SNAS589D – JUNE 2012 – REVISED MAY 2013 LMK04906 Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs Check for Samples: LMK04906 FEATURES APPLICATIONS • • • 1 23 • • • • • • • • • •

Contextual Info: LMK04816 www.ti.com SNAS597A – JULY 2012 – REVISED AUGUST 2012 LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04816 FEATURES 1 • Ultra-Low RMS Jitter Performance – 100 fs RMS jitter 12 kHz to 20 MHz