SPI MASTER Search Results

Contextual Info: Active Errata List • • • • During UART Reception, Clearing REN May Generate Unexpected IT SPI Interface - Transmission on Master Mode SPI Interface - SPI SS pin Limitation on Master/Slave SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the

AT80C51ID2

Abstract: spi slave atmel 8051 datasheet 80C51 AT80C51RD2 AT83C51RB2 AT83C51RC2 Atmel AT80 AT83C51IC2
Contextual Info: Active Errata List • • • • During UART Reception, Clearing REN May Generate Unexpected IT SPI Interface - Transmission on Master Mode SPI Interface - SPI SS pin Limitation on Master/Slave SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the

JTAG MODULE SPI

Abstract: spi flash parallel port TSOP 28 SPI memory Package flash 88P8341
Contextual Info: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors

IDT88P8344

Abstract: 88P8344
Contextual Info: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors

TSOP 48 thermal resistance type1

Abstract: IDT88P8342 drw22
Contextual Info: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors

Contextual Info: PRODUCT BRIEF IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation

spi FIFO

Abstract: IDT88P8344 DSC-6370
Contextual Info: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation

spi on parallel port

Abstract: IDT88P8342
Contextual Info: PRODUCT BRIEF IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation

software uart SC16IS740

Abstract: UART abstract AN10428 UART-SPI gateway Philips slave bridges SPI to RS232 SC16IS740 UART-SPI Gateway for Philips SPI slave bridges spi slave cable gateway reference design spi In Circuit Serial Programming
Contextual Info: AN10428 UART-SPI Gateway for Philips SPI slave bridges Rev. 01 — 7 March 2006 Application note Document information Info Content Keywords UART-SPI Gateway, UART to SPI, RS-232 to SPI Abstract The UART-SPI Gateway enables a PC that has a UART port to communicate with a SPI slave device using an RS-232 terminal. With the

AVR319

Abstract: AVR310 atmega128 SPI code example Application Note ATTINY2313
Contextual Info: AVR319: Using the USI module for SPI communication 8-bit Microcontrollers Features • C-code driver for SPI master and slave • Uses the USI module • Supports SPI Mode 0 and 1 Application Note Introduction The Serial Peripheral Interface SPI allows high-speed synchronous data transfer

AVR151

Abstract: AVR910 SCK 104 avr spi ICE200 STK500
Contextual Info: AVR151: Setup And Use of The SPI Features • • • • • • • SPI Pin Functionality Multi Slave Systems SPI Timing SPI Transmission Conflicts Emulating the SPI Code examples for Polled operation Code examples for Interrupt Controlled operation 8-bit RISC

cheetah

Abstract: Leopard Logic WIN32
Contextual Info: Cheetah SPI Host Adapter Features • SPI Master • Full Duplex SPI at 40 MHz • Unsupported Overclocking up to 50 MHz • All Modes Supported • High-Speed USB Device 480 Mbps transfer to host PC • Actual Host Data Throughput Nearly 100% of SPI Clock Rate

AVR1309: Using the XMEGA SPI

Abstract: AVR1309 xmega MOSI MEANING spi operation xmega usb
Contextual Info: AVR1309: Using the XMEGA SPI Features • Introduction to SPI and the XMEGA SPI module • Setup and use of the XMEGA SPI module • Implementation of module drivers Polled master Interrupt controlled master Polled slave Interrupt controlled slave • Code examples for interrupt controlled and polled drivers

LatticeMico32

Contextual Info: LatticeMico SPI The LatticeMico serial peripheral interface SPI provides an industrystandard interface between a LatticeMico32 processor and off-chip peripherals, as shown in Figure 1. In master mode, the SPI can be configured to control communication with up to 32 off-chip SPI ports. In slave mode, the

Contextual Info: PSoC Creator Component Datasheet Serial Peripheral Interface SPI Master 2.20 Features • 3- to 16-bit data width • Four SPI operating modes  Bit rate up to 9 Mbps1 General Description The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can

psoc full projects

Contextual Info: PSoC Creator Component Datasheet Serial Peripheral Interface SPI Master 2.30 Features • 3- to 16-bit data width • Four SPI operating modes  Bit rate up to 18 Mbps* General Description The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can

AVR151

Abstract: AVR910 ICE200 STK500
Contextual Info: AVR151: Setup And Use of The SPI Features • • • • • • • SPI Pin Functionality Multi Slave Systems SPI Timing SPI Transmission Conflicts Emulating the SPI Code examples for Polled operation Code examples for Interrupt Controlled operation 8-bit RISC

cypress flash 370

Contextual Info: PSoC Creator Component Datasheet Serial Peripheral Interface SPI Master 2.40 Features • 3- to 16-bit data width • Four SPI operating modes  Bit rate up to 18 Mbps* General Description The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can

0x1113

Contextual Info: PSoC Creator Component Data Sheet Serial Peripheral Interface SPI Master 2.0 Features • 2- to 16-bit data width • 4 SPI operating modes • Data rates to 33 Mb/s General Description The SPI Master component provides an industry-standard 4-wire master SPI interface, as well

SC18IM700

Abstract: RS-232 to i2c converter sc18is602ipw I2C master controller uart i2c to RS-232 converter LCD 16PIN 4 SC18IS600 SC18IS600IPW SC18IS601 SC18IS602
Contextual Info: NXP I2C/SPI master bridges SC18IS600/601, SC18IS602/603, and SC18IM700 Connect I2C/SPI slave or UART to I2C/SPI master or GPIO These compact protocol converters create seamless, low-power, low-voltage interface connections, so they make it quick and easy to add I2C/SPI master and GPIO capability to

SCA1020

Abstract: sca1000 SCA100T spi 3 wire SCA103T SCA61T
Contextual Info: Technical Note 15 1 5 SPI Interface Specification OBJECTIVE This document specifies the Serial Peripheral Interface (SPI) that is used in the SCA61T, SCA100T, SCA103T, SCA1000, and SCA1020 –series sensors. THE SPI INTERFACE A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave devices. The

80C51

Abstract: T89C51RB2 T89C51RC2
Contextual Info: Active Errata List • • • • • • • • • • During UART Reception, Clearing REN May Generate Unexpected IT Internal Resistor on Reset Pin SPI – SPI SS Pin Limitation on Master/Slave SPI – SPI Slave Responding in a Multislave Configuration When Not Selected by the

Contextual Info: PSoC Creator Component Data Sheet Serial Peripheral Interface SPI Master 2.10 Features • 3- to 16-bit data width  4 SPI operating modes  Bit Rate up to 9 Mbps * General Description The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can

M95512 diagram

Abstract: M95512-DR M95512-W M95512 M95512-R
Contextual Info: M95512-DR M95512-R M95512-W 512 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes : – M95512-W and M95512-R: standard SPI 512 Kbit EEPROM – M95512-DR: standard SPI 512 Kbit