SN74SSTU32864CGKER Search Results

SN74SSTU32864CGKER Datasheets (3)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
SN74SSTU32864CGKER		Texas Instruments	SN74SSTU32864 - IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96, FF/Latch	Original	PDF	784.29KB	19
SN74SSTU32864CGKER		Texas Instruments	25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS	Original	PDF	304.69KB	18
SN74SSTU32864CGKER		Texas Instruments	25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70	Original	PDF	478.23KB	20

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SN74SSTU32864CGKER Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
A115-A Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542A 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER	PDF
A115-A Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
A115-A Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER	PDF
SSTL-18 Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit SSTL-18	PDF
S864C Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit S864C	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF
A115-A Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER Contextual Info: SN74SSTU32864C 25ĆBIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES542 − JANUARY 2004 D Member of the Texas Instruments D D D D D D D Supports LVCMOS Switching Levels on the Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout	Original	SN74SSTU32864C 25BIT SCES542 25-Bit 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER	PDF
Contextual Info: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout	Original	SN74SSTU32864C 25-BIT SCES542B 14-Bit	PDF