SN74S10 Search Results

SN74LS10

Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN74S1056 8-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY _SDLS019B- APRIL 1990 - REVISED JULY 1997 Designed to Reduce Reflection Noise SC PACKAGE TOP VIEW Repetitive Peak Forward Current 300 mA 8-Bit Array Structure Suited for Bus-Oriented Systems

Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3 INPUT POSITIVE NAND GATES D EC EM B ER 1 9 8 3 -R E V IS E O M A R C H 1 9 8 8 Package O ptions Include Plastic "Sm a ll O utline" Packages, Ceram ic Chip Carriers and Flat Packages, and Plastic and Ceram ic

Contextual Info: SN74S1053 16-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997 D D D D DW OR N PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 16-Bit Array Structure Suited for

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74S1052DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1052DWE4

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74S1052DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1052DWE4 ACTIVE

SN7410N

Abstract: chip sn7410 JM38510 TEXAS INSTRUMENTS
Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

SN5410

Abstract: SN54LS10 SN54S10 SN7410 SN74LS10 SN74S10 00103BC
Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

M38510

Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) SN74S1052DW ACTIVE SOIC DW 20

Contextual Info: SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

SN74S1053

Abstract: SN74S1053DBR SN74S1053DBRE4 SN74S1053DW SN74S1053DWG4 SN74S1053DWR SN74S1053DWRG4 SN74S1053N
Contextual Info: SN74S1053 16-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997 D D D D DW OR N PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 16-Bit Array Structure Suited for

SN74S1050D

Abstract: SN74S1050DR SN74S1050N
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74S1050D ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/

Contextual Info: SN74S1053 16-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997 D D D D DW OR N PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 16-Bit Array Structure Suited for

SN74S1052DW

Abstract: SN74S1052DWE4 SN74S1052DWG4 SN74S1052N SN74S1052NE4 SN74S1052NSR SN74S1052NSRE4 SN74S1052NSRG4
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74S1052DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1052DWE4

Moisture Sensitivity Level Rating

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74S1050D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1050DE4 ACTIVE

irm 38

Contextual Info: SN74S1053 16-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997 D D D D DW OR N PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 16-Bit Array Structure Suited for

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74S1050D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1050DE4 ACTIVE

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

EBV diode

Contextual Info: SN74S1053 16-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997 D D D D DW OR N PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 16-Bit Array Structure Suited for