SN74LV373 Search Results

Contextual Info: SN74LV373AĆQ1 OCTAL TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCLS586B − JUNE 2004 − REVISED APRIL 2005 D Qualification in Accordance With DW OR PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407G – APRIL 1998 – REVISED OCTOBER 2002 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1Q 1D 2D 2Q 3Q 3D 4D 4Q 20 1D 1Q OE VCC 8Q 1 SN54LV373A . . . FK PACKAGE

Contextual Info: SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22

54LV373

Contextual Info: SN54LV373, SN74LV373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS _SCLS196C - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-\i Process SN54LV373 . . . J OR W PACKAGE SN74LV373. . . DB, DW, OR PW PACKAGE

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407G – APRIL 1998 – REVISED OCTOBER 2002 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1Q 1D 2D 2Q 3Q 3D 4D 4Q 20 1D 1Q OE VCC 8Q 1 SN54LV373A . . . FK PACKAGE

Contextual Info: SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 FEATURES 1 • • • • • • • • PW PACKAGE TOP VIEW Qualified for Automotive Applications 2-V to 5.5-V VCC Operation Maximum tpd of 8.5 ns at 5 V

Contextual Info: SN54LV373, SN74LV373 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS196C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C

lv373

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22

Contextual Info: SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 FEATURES 1 • • • • • • • • PW PACKAGE TOP VIEW Qualified for Automotive Applications 2-V to 5.5-V VCC Operation Maximum tpd of 8.5 ns at 5 V

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

SN54LV373A

Abstract: SN74LV373A A115-A C101
Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407I − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22

SN54LV373

Abstract: SN74LV373 2811Q
Contextual Info: SN54LV373, SN74LV373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS196C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

SN74LV373

Abstract: SN54LV373
Contextual Info: SN54LV373, SN74LV373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS196C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C

Contextual Info: SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22

A115-A

Abstract: C101 SN54LV373A SN74LV373A
Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407B – APRIL 1998 – REVISED MAY 2000 D D D D D D description The ’LV373A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. SN54LV373A . . . J OR W PACKAGE

Contextual Info: SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22

SN74LV373

Contextual Info: SN74LV373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS _ SCLS196 -FEBRUARY 1993-R EV ISE D MARCH 1994 • EPIC Enhanced-Performance Implanted CMOS 2-(i Process • Typical Vq l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C