SN74LV125 Search Results

LV125A

Abstract: 74lv125a A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124F – DECEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

SN74LV125

Contextual Info: SN74LV125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES003A- NOVEMBER 1 9 9 4 - REVISED JULY 1996 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) 2-ii Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A 74LV125
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124J – DECEMBER 1997 – REVISED JULY 2003 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6

Contextual Info: SN74LV125A-Q1 www.ti.com SCES814 – SEPTEMBER 2010 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS Check for Samples: SN74LV125A-Q1 FEATURES 1 • • 1A 1Y 2OE 2A 2Y VCC RGY PACKAGE TOP VIEW 1 14 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6 GND 7 8 3Y • Qualified for Automotive Applications

LV125A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124I – DECEMBER 1997 – REVISED OCTOBER 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124I – DECEMBER 1997 – REVISED OCTOBER 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 FEATURES • • • • • • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 3.8 ns at 5 V Typical VOLP Output Ground Bounce

Contextual Info: SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 FEATURES • • • • • • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 3.8 ns at 5 V Typical VOLP Output Ground Bounce

LV125A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124A - DECEMBER 1997 - REVISED MARCH 1998 EPICM Enhanced-Performance Implanted CMOS Process SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124C - DECEMBER 1997 - REVISED MAY 1998 EPIC * Enhanced-Performance Implanted CMOS Process SN54LV125A . . . J O f i W PACKAGE SN74L.V125A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2

Contextual Info: SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 FEATURES • • • • • • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 3.8 ns at 5 V Typical VOLP Output Ground Bounce

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124I – DECEMBER 1997 – REVISED OCTOBER 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A 74LV125a
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

lv125a

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125, SN74LV125 QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 SN54LV125 . . . J OR W PACKAGE SN74LV125 . . . D, DB, OR PW PACKAGE TOP VIEW D EPIC ( Enhanced-Performance Implanted D D D D 1OE 1A

LV125

Abstract: LV-125
Contextual Info: SN54LV125, SN74LV125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES0Q3B- NOVEMBER 1994 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0 .8 V a tV c c ,T A = 25oC Typical Vqhv (Output Vqh Undershoot)

A115-A

Abstract: C101 SN74LV125AT SN74LV125ATD SN74LV125ATRGYR
Contextual Info: SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 FEATURES • • • • • • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 3.8 ns at 5 V Typical VOLP Output Ground Bounce

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A