SN74ACT2 Search Results

Contextual Info: SN74ACT2235 1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148E - DECEMBER 1990 - REVISED APRIL 1998 • Independent Asynchronous Inputs and Outputs • Access Times of 25 ns With a 50-pF Load • Data Rates up to 50 MHz • Low-Power Advanced CMOS Technology

Contextual Info: SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS516B – JUNE 1995 – REVISED MAY 1996 D SN54ACT241 . . . J OR W PACKAGE SN74ACT241 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN74ACT2158, SN74ACT2159 8K x 9 CACHE ADDRESS COMPARATORS/DATA RAMs D 3 2 8 1 , M A Y 1 9 9 0 R E V IS E D J U N E 1990 Fast Address to MATCH Delay 22 ns Max FN PACKAGE TOP VIEW 8K x 10 Internal Static RAM ISCI 5 Ä • Word Reset Function for Single Entry

SN74ACT244MNSREP

Contextual Info: SN74ACT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS724B – OCTOBER 2003 – REVISED MARCH 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of up to

SN54ACT245

Abstract: SN74ACT245 SN74ACT245DBR SN74ACT245DW SN74ACT245DWR SN74ACT245N SN74ACT245NSR SN74ACT245PWR SNJ54ACT245J SN74ACT245PWLE
Contextual Info: SN54ACT245, SN74ACT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS452E – SEPTEMBER 1994 – REVISED OCTOBER 2002 D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 8 ns at 5 V Inputs Are TTL-Voltage Compatible SN54ACT245 . . . J OR W PACKAGE

Contextual Info: SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS516C – JUNE 1995 – REVISED OCTOBER 2002 D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 8.5 ns at 5 V Inputs Are TTL Compatible SN54ACT241 . . . FK PACKAGE

Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

ACT29116

Abstract: 2NACC Y15V CMOS 16-Bit Priority Encoder block diagram for barrel shifter Am29116
Contextual Info: ^ lOrrf?- SN74ACT29116, SN74ACT29116-1 16-BIT MICROPROCESSOR D 2 9 6 2 , SEPTEMBER 1 9 8 7 • 1 pm EPIC {Enhanced Performance Implanted CMOS CMOS Technology • 32-Bit Register File Can Be Written and Read During a Single Cycle • 16-Bit Barrel Shifter Can Shift Up to

62d18

Abstract: fifo ttl B129 B249 SN74ACT2226 SN74ACT2228
Contextual Info: SN74ACT2226, SN74ACT2228 DUAL 6 4 x 1 AND DUAL 256x1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219A - JUNE 1992-R E V IS E D AUGUST 1993 Dual Independent FIFOs Organized as: - 64 Words by 1 Bit Each - SN74ACT2226 - 256 Words by 1 Bit Each - SN74ACT2228 Free-Running Read and Write Clocks Can

Contextual Info: SN54ACT244, SN74ACT244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS517C − JUNE 1995 − REVISED OCTOBER 2002 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL Compatible SN54ACT244 . . . J OR W PACKAGE

SN74ACT2152

Abstract: SN74ACT2154 SN74ACT2152A
Contextual Info: SN74ACT2152A, SN74ACT2154A 2K x 8 CACHE ADDRESS COMPARATORS D 3 1 5 6 , DECEMBER 1 9 8 8 -R E V IS E D MARCH 1 9 9 0 • • N PACKAGE Fast Address to Match Delay 2 0 or 2 5 ns Max TOP VIEW RESET C 1 ^ 2 8 Common I/O w ith Read Feature A4 C 2 H A5 27 1 A 6

D3365

Abstract: SN74ACT2160
Contextual Info: SN74ACT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/DATA RAM D3365, JANUARY 1990-REVISED JUNE 1990 Address to Match Time . . . 1 7 n s Max FM PACKAGE TOP VIEW 2-Way Architecture Significantly Improves Hit Rate KT> CO C\J 1 - O < < < < < < O O y L J P C J L J L J a n

Contextual Info: SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS149A- APRIL 1990 - REVISED SEPTEMBER 1995 I n d e p e n d e n t A s y n c h r o n o u s I nput s and Outputs A c c e s s T i m e s o f 2 5 ns With a 5 0 -pF Load L o w - P o w e r A d v a n c e d C M O S T e c hn o l o g y

16-1 multiplexer explain

Abstract: AM29C116-1
Contextual Info: fO 'ï'-ti? - SN74ACT29116, SN74ACT29116-1 16 BIT MICROPROCESSOR D 2 9 6 2 , SEPTEMBER 1 9 8 7 • 1 pm EPIC Enhanced Performance Implanted CMOS CMOS Technology • 32-Bit Register File Can Be Written and Read During a Single Cycle • 16-Bit Barrel Shifter Can Shift Up to

SN74ACT2235

Abstract: SN74ACT2236
Contextual Info: SN74ACT2236 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS149A – APRIL 1990 – REVISED SEPTEMBER 1995 D D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional 1024 Words by 9 Bits Each

Contextual Info: SN74ACT2227, SN74ACT2229 DUAL 64 x 1, DUAL 256 × 1 FIRST-IN, FIRST-OUT MEMORIES SCAS220C – JUNE 1992 – REVISED OCTOBER 1997 D D D D D D D D D D Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each – SN74ACT2227 256 Words by 1 Bit Each – SN74ACT2229

MS-013

Abstract: MSOI003E SN74ACT244 SN74ACT244MDWREP
Contextual Info: SN74ACT244ĆEP OCTAL BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SCAS724 − OCTOBER 2003 D Controlled Baseline D D D D D D Inputs Accept Voltages to 5.5 V D Max tpd of 9.5 ns at 5 V D Inputs Are TTL Compatible − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

B129

Abstract: B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Contextual Info: SN74ACT2227, SN74ACT2229 DUAL 64 x 1, DUAL 256 × 1 FIRST-IN, FIRST-OUT MEMORIES SCAS220C – JUNE 1992 – REVISED OCTOBER 1997 D D D D D D D D D D Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each – SN74ACT2227 256 Words by 1 Bit Each – SN74ACT2229

Contextual Info: SN54ACT244, SN74ACT244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS517C – JUNE 1995 – REVISED OCTOBER 2002 D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V SN54ACT244 . . . J OR W PACKAGE SN74ACT244 . . . DB, DW, N, NS, OR PW PACKAGE

Contextual Info: SN74ACT2226, SN74ACT2228 DUAL 64 x 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 D D D D D D D D D Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each – SN74ACT2226 256 Words by 1 Bit Each – SN74ACT2228

Contextual Info: SN74ACT244ĆQ1 OCTAL BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SCAS766A − APRIL 2004 − REVISED JUNE 2004 D Qualification in Accordance With PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D

MS-018

Abstract: SN74ACT2235
Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

SN74ACT2235

Abstract: SN74ACT2235-20FN SN74ACT2235-20PAG SN74ACT2235-20PM
Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

74ACT21

Abstract: SN74ACT2155
Contextual Info: SN74ACT2155 2K x 8 BURST CACHE ADDRESS COMPARATORJDATA RAM D 3 0 7 6 , N O V E M B E R 1 9 8 8 - R E V IS E D J U N E 1 9 9 0 • Address to MATCH Time . . . 2 2 ns Max • Supports Motorola M C 6 8 0 3 0 Cache Burst Fill with No Added W ait States FN PACKAGE